Yoshiki Saito

Publication Activity (10 Years)

Years Active: 2008-2012
Publications (10 Years): 0

Top Topics

Synthetic Aperture Radar

Change Detection

Top Venues

Publications

Akiko Tanaka, Katsuto Uehara, Toru Tamura, Yoshiki Saito
Area change detection in river mouthbars at the Mekong River delta using Synthetic Aperture Radar (SAR) data. IGARSS (2012)
Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC (2011)
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT (2011)
Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31 (6) (2011)
Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT (2010)
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano
MuCCRA-3: a low power dynamically reconfigurable processor array. ASP-DAC (2010)
Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano
Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS (2009)
Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano
Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. FPT (2009)
Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. FPL (2009)
Toru Sano, Yoshiki Saito, Hideharu Amano
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. ERSA (2009)
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. ERSA (2009)
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano
Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL (2008)
Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT (2008)