Kazuei Hironaka

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 18

Top Topics

Fpga Implementation

Message Passing

Top Venues

IEICE Trans. Inf. Syst.

CANDAR (Workshops)

Publications

M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search. IEICE Trans. Inf. Syst. 106 (11) (2023)
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters. IEICE Trans. Inf. Syst. 106 (12) (2023)
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System. IEICE Trans. Inf. Syst. (12) (2022)
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
Power Analysis of Directly-connected FPGA Clusters. COOL CHIPS (2022)
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems. MCSoC (2022)
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. COOL CHIPS (2021)
Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano
M-KUBOS/PYNQ Cluster for multi-access edge computing. CANDAR (2021)
Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud). IEICE Trans. Inf. Syst. (8) (2021)
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
Implementing VTA, a tensor accelerator on Flow-in-Cloud. ACIT (2021)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. (12) (2021)
Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano
A Method of Partitioning Convolutional Layer to Multiple FPGAs. ISOCC (2020)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) (2020)
Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system. CANDAR (Workshops) (2020)
Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano
Demonstration of Flow-in-Cloud: A Multi-FPGA System. FPL (2019)
Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano
The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW. HEART (2019)
Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano
Multi-FPGA Management on Flow-in-Cloud Prototype System. SNPD (2019)
Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. MCSoC (2019)
Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study. ARC (2018)
Toru Katagiri, Kazuei Hironaka, Hideharu Amano
Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array. NBiS (2012)
Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami
Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. ARC (2011)
Kazuei Hironaka, Hideharu Amano
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth. ReConFig (2011)
Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano
The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator. FPT (2011)
Masayuki Kimura, Kazuei Hironaka, Hideharu Amano
Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. FPT (2011)
Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT (2010)