Sign in
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System.
Kohei Ito
Kensuke Iizuka
Kazuei Hironaka
Yao Hu
Michihiro Koibuchi
Hideharu Amano
Published in:
IEICE Trans. Inf. Syst. (2021)
Keyphrases
</>
high speed
interconnection networks
power reduction
real time
fault tolerant
message passing
gate array
logic circuits
low cost
multistage
parallel algorithm
hardware implementation
field programmable gate array
computer science
pairwise
graphical models