Hideharu Amano

ORCID

Publication Activity (10 Years)

Years Active: 1983-2024
Publications (10 Years): 207

Top Venues

IEICE Trans. Inf. Syst.

MCSoC

CANDAR

FPL

Publications

Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS (2024)
Hideharu Amano, Kensuke Iizuka
Power analysis of an optical interconnected FPGA cluster for roadside units. ICCE (2024)
Zirui Lin, Katsutoshi Itoyama, Kazuhiro Nakadai, Hideharu Amano
FPGA-based Low Power Acceleration of HARK Sound Source Localization. COOL CHIPS (2024)
Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano
Power Optimized Design Framework for FPGA Clusters. IPSJ Trans. Syst. LSI Des. Methodol. 17 (2024)
Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi
A data compressor for FPGA-based state vector quantum simulators. HEART (2024)
Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. IEEE Trans. Very Large Scale Integr. Syst. 32 (1) (2024)
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano
A cost/power efficient storage system with directly connected FPGA and SATA disks. MCSoC (2023)
Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages. ICFPT (2023)
Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi
A Compression Router for Low-Latency Network-on-Chip. IEICE Trans. Inf. Syst. 106 (2) (2023)
Hideharu Amano
Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing. HEART (2023)
Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai
Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board. COOL CHIPS (2023)
M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search. IEICE Trans. Inf. Syst. 106 (11) (2023)
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
Parallel Implementation of CNN on Multi-FPGA Cluster. IEICE Trans. Inf. Syst. 106 (7) (2023)
Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. 35 (11) (2023)
Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano
A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. IEEE Micro 43 (1) (2023)
Takumi Inage, Kensuke Iizuka, Hideharu Amano
Board Allocation Algorithm for the Resource Management System of FiC. MCSoC (2023)
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability. IEICE Trans. Inf. Syst. 106 (3) (2023)
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster. candar (2023)
Haris Gulzar, Muhammad Shakeel, Katsutoshi Itoyama, Kazuhiro Nakadai, Kenji Nishida, Hideharu Amano, Takeharu Eda
FPGA based Power-Efficient Edge Server to Accelerate Speech Interface for Socially Assistive Robotics. SII (2023)
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters. IEICE Trans. Inf. Syst. 106 (12) (2023)
Kaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi
A state vector quantum simulator working on FPGAs with extensible SATA storage. ICFPT (2023)
Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano
Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations. NorCAS (2022)
Yuchen Chen, Kaijie Wei, Hiroaki Nishi, Hideharu Amano
An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board. CANDAR (2022)
Zhongyang Hou, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai
An FPGA off-loading of HARK sound source localization. CANDARW (2022)
Shigeyuki Takano, Hideharu Amano
Reconfiguration Cost for Reconfigurable Computing Architectures. SNPD-Summer (2022)
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System. IEICE Trans. Inf. Syst. (12) (2022)
Aoi Hiruma, Kensuke Iizuka, Hideharu Amano
Toward a training of CNNs on a multi-FPGA system. CANDARW (2022)
Kohei Ito, Ryota Yasudo, Hideharu Amano
Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches. FPL (2022)
Morihiro Kuga, Masahiro Iida, Hideharu Amano
FPL Demo: An FPGA-IP Prototype Chip for MEC devices. FPL (2022)
Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano
A Hardware Trojan Exploiting Coherence Protocol on NoCs. PDCAT (2022)
Ayaka Ohwada, Takuya Kojima, Hideharu Amano
An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings. PDP (2022)
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90 (2022)
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
Power Analysis of Directly-connected FPGA Clusters. COOL CHIPS (2022)
Naoya Niwa, Hideharu Amano, Michihiro Koibuchi
Boosting the Performance of Interconnection Networks by Selective Data Compression. IEICE Trans. Inf. Syst. (12) (2022)
Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano
Body Bias Control on a CGRA based on Convex Optimization. COOL CHIPS (2022)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA. Int. J. Netw. Comput. 12 (2) (2022)
Takuya Kojima, Ayaka Ohwada, Hideharu Amano
Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning. IEEE Trans. Parallel Distributed Syst. 33 (5) (2022)
Zhou Yuqing, Naoya Niwa, Hideharu Amano
Distance Aware Compression for Low Latency High Bandwidth Interconnection Network. MCSoC (2022)
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems. MCSoC (2022)
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. HEART (2022)
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR (2022)
Pengyu Huang, Kaijie Wei, Hideharu Amano, Kaori Ohkoda, Masashi Aono
Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory. CANDARW (2022)
Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops. MCSoC (2021)
Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi
A Case for Low-Latency Network-on-Chip using Compression Routers. PDP (2021)
Hideto Kayashima, Hideharu Amano
Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface. CANDAR (Workshops) (2021)
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. COOL CHIPS (2021)
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT (2021)
Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano
Parallel Implementation of CNN on Multi-FPGA Cluster. MCSoC (2021)
Kaijie Wei, Koki Honda, Hideharu Amano
An implementation methodology for Neural Network on a Low-end FPGA Board. Int. J. Netw. Comput. 11 (2) (2021)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA. CANDAR (Workshops) (2021)
Hideto Kayashima, Hideharu Amano
TCI Tester: Tester for Through Chip Interface. ASP-DAC (2021)
Takeharu Ikezoe, Takuya Kojima, Hideharu Amano
Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures. IEICE Trans. Electron. (6) (2021)
Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool. HEART (2021)
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP (2021)
Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms. ACM Trans. Reconfigurable Technol. Syst. 14 (3) (2021)
Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano
M-KUBOS/PYNQ Cluster for multi-access edge computing. CANDAR (2021)
Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud). IEICE Trans. Inf. Syst. (8) (2021)
Sannomiya Natsuho, Takeshi Ohkawa, Hideharu Amano, Midori Sugaya
Power Consumption Reduction Method and Edge Offload Server for Multiple Robots. EDGE (2021)
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
Implementing VTA, a tensor accelerator on Flow-in-Cloud. ACIT (2021)
Ying Jie Yan, Hideharu Amano, Masashi Aono, Kaori Ohkoda, Shingo Fukuda, Kenta Saito, Seiya Kasai
Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim. FPT (2021)
Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. (12) (2021)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis. IEICE Trans. Inf. Syst. (12) (2021)
Miho Yamakura, Ryousei Takano, Akram Ben Ahmed, Midori Sugaya, Hideharu Amano
A Multi-Tenant Resource Management System for Multi-FPGA Systems. IEICE Trans. Inf. Syst. (12) (2021)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. (12) (2021)
Naoya Niwa, Hideharu Amano, Michihiro Koibuchi
Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression. CANDAR (2021)
Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa
FPGA Acceleration of ROS2-Based Reinforcement Learning Agents. CANDAR (Workshops) (2020)
Kaijie Wei, Koki Honda, Hideharu Amano
An implementation methodology for Neural Network on a Low-end FPGA Board. CANDAR (2020)
Yuxi Sun, Hideharu Amano
FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks. IEICE Trans. Inf. Syst. (12) (2020)
Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP (2020)
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. CANDAR (Workshops) (2020)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. (12) (2020)
M. M. Imdad Ullah, Akram Ben Ahmed, Hideharu Amano
Implementation of FM-Index Based Pattern Search on a Multi-FPGA System. ARC (2020)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. (1) (2020)
Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano
A Method of Partitioning Convolutional Layer to Multiple FPGAs. ISOCC (2020)
Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa
Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems. FPT (2020)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) (2020)
Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system. CANDAR (Workshops) (2020)
Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. COOL CHIPS (2020)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
CLAHE implementation on a low-end FPGA board by high-level synthesis. CANDAR (Workshops) (2020)
Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter
Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation. ACM J. Emerg. Technol. Comput. Syst. 16 (3) (2020)
Manfred Orsztynowicz, Hideharu Amano, Kenichi Kubota, Takaaki Miyajima
Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA. CANDAR (2020)
Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano
An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation. HEART (2019)
Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano
Key-value Store Chip Design for Low Power Consumption. COOL CHIPS (2019)
Koki Honda, Kaijie Wei, Hideharu Amano
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board. MCSoC (2019)
Ryosuke Kazami, Hideharu Amano
A Rapid Optimization Method for Visual Indirect SLAM Using a Subset of Feature Points. CANDAR Workshops (2019)
Yugo Yamauchi, Kazusa Musha, Hideharu Amano
Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud. COOL CHIPS (2019)
Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter
Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation. CoRR (2019)
Yuxi Sun, Akram Ben Ahmed, Hideharu Amano
Acceleration of Deep Recurrent Neural Networks with an FPGA cluster. HEART (2019)
Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki
A Preliminary Evaluation of Building Block Computing Systems. MCSoC (2019)
Takeharu Ikezoe, Takuya Kojima, Hideharu Amano
A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable Memory. FPT (2019)
Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano
Demonstration of Flow-in-Cloud: A Multi-FPGA System. FPL (2019)
Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano
The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW. HEART (2019)
Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano
Multi-FPGA Management on Flow-in-Cloud Prototype System. SNPD (2019)
Takuya Kojima, Hideharu Amano
A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures. IEICE Trans. Inf. Syst. (7) (2019)
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. 30 (2) (2019)
Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano
Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process. CANDAR Workshops (2019)
Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. MCSoC (2019)
Yasuaki Okamoto, Hideharu Amano
Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel. CANDAR Workshops (2019)

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Publication Activity (10 Years)

Top Topics

Top Venues

Hideharu Amano