Morihiro Kuga

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 17

Top Topics

Hardware Implementation

Hardware Architectures

Top Venues

IEICE Trans. Inf. Syst.

Publications

Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS (2024)
Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida
An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Morihiro Kuga, Masahiro Iida, Hideharu Amano
FPL Demo: An FPGA-IP Prototype Chip for MEC devices. FPL (2022)
Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga
Automation of Domain-specific FPGA-IP Generation and Test. HEART (2021)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. (2) (2018)
Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT (2017)
Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. (4) (2017)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. 10 (2017)
Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
High-level Synthesis based on Parallel Design Patterns using a Functional Language. HEART (2017)
Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
FPGA based ASIC Emulator with High Speed Optical Serial Links. HEART (2017)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44 (4) (2016)
Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
hCODE: An open-source platform for FPGA accelerators. FPT (2016)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. (2) (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Simple wafer stacking 3D-FPGA architecture. ICICDT (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. 10 (3) (2015)
Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC (2015)
Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Blokus Duo engine on a Zynq. FPT (2014)
Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Zyndroid: An Android platform for software/hardware coprocessing. FPT (2014)
Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL (2014)
Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC (2013)
Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA (2013)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. (8) (2013)
Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
A reconfigurable Java accelerator with software compatibility for embedded systems. SIGARCH Comput. Archit. News 41 (5) (2013)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
An automatic FPGA design and implementation framework. FPL (2013)
Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. ICA3PP (1) (2012)
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel physical defects recovery technique for FPGA-IP cores. ReConFig (2012)
Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. FPT (2012)
Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. FCCM (2012)
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC (2012)
Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Fault detection and avoidance of FPGA in various granularities. FPL (2012)
Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. ICA3PP (1) (2012)
Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Improving the Soft-error Tolerability of a Soft-core Processor on. J. Next Gener. Inf. Technol. 2 (3) (2011)
Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
Parallelization of the channel width search for FPGA routing. SIGARCH Comput. Archit. News 39 (4) (2011)
Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Power-aware FPGA routing fabrics and design tools. VLSI-SoC (2010)
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM (2010)
Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
Memory Sharing Approach for TMR Softcore Processor. ARC (2009)
Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
A novel states recovery technique for the TMR softcore processor. FPL (2009)
Hidetomo Shibamura, Masayuki Fukuyama, Daisuke Uchida, Seiji Ikeda, Morihiro Kuga, Toshinori Sueyoshi
EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA. FPT (2004)
Toshinori Sueyoshi, Morihiro Kuga, Hidetomo Shibamura
KITE microprocessor and CAE for computer science. Systems and Computers in Japan 33 (8) (2002)
Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN (1994)
Morihiro Kuga, Kazuaki J. Murakami, Shinji Tomita
DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture. SIGARCH Comput. Archit. News 19 (4) (1991)
Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ISCA (1989)