A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory.
Qian ZhaoKyosei YanagidaMotoki AmagasakiMasahiro IidaMorihiro KugaToshinori SueyoshiPublished in: FPL (2014)
Keyphrases
- information theory
- management system
- random access memory
- real time
- memory size
- memory usage
- reasoning engine
- computing power
- memory management
- logic programming
- memory requirements
- memory hierarchy
- design considerations
- embedded dram
- application level
- limited memory
- reduction method
- modal logic
- logical framework
- multi valued
- computational power
- deontic logic
- data flow
- associative memory
- logic programs