Toshinori Sueyoshi

Publication Activity (10 Years)

Years Active: 1985-2018
Publications (10 Years): 18

Top Topics

Hardware Architectures

Hardware Implementation

Top Venues

IEICE Trans. Inf. Syst.

Publications

Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
Three Dimensional FPGA Architecture with Fewer TSVs. IEICE Trans. Inf. Syst. (2) (2018)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. (2) (2018)
Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT (2017)
Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. (4) (2017)
Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
A Study of FPGA Virtualization and Accelerator Scheduling. ETCD@ASPLOS (2017)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. 10 (2017)
Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
High-level Synthesis based on Parallel Design Patterns using a Functional Language. HEART (2017)
Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
FPGA based ASIC Emulator with High Speed Optical Serial Links. HEART (2017)
Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi
An area compact soft error resident circuit for FPGA. ICICDT (2016)
Motoki Amagasaki, Ryo Araki, Masahiro Iida, Toshinori Sueyoshi
SLM: A Scalable Logic Module Architecture with Less Configuration Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44 (4) (2016)
Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
hCODE: An open-source platform for FPGA accelerators. FPT (2016)
Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi
A novel soft error tolerant FPGA architecture. VLSI-SoC (2016)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. (2) (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Simple wafer stacking 3D-FPGA architecture. ICICDT (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. 10 (3) (2015)
Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC (2015)
Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi
A novel three-dimensional FPGA architecture with high-speed serial communication links. FPT (2014)
Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Blokus Duo engine on a Zynq. FPT (2014)
Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Zyndroid: An Android platform for software/hardware coprocessing. FPT (2014)
Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL (2014)
Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC (2013)
Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA (2013)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. (8) (2013)
Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
A reconfigurable Java accelerator with software compatibility for embedded systems. SIGARCH Comput. Archit. News 41 (5) (2013)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
An automatic FPGA design and implementation framework. FPL (2013)
Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. ICA3PP (1) (2012)
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel physical defects recovery technique for FPGA-IP cores. ReConFig (2012)
Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. FPT (2012)
Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. FCCM (2012)
Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi
COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Trans. Inf. Syst. (2) (2012)
Shunsuke Oshima, Takuo Nakashima, Toshinori Sueyoshi
The Evaluation of an Anomaly Detection System Based on Chi-square Method. AINA Workshops (2012)
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC (2012)
Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
An Easily Testable Routing Architecture and Prototype Chip. IEICE Trans. Inf. Syst. (2) (2012)
Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Fault detection and avoidance of FPGA in various granularities. FPL (2012)
Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. ICA3PP (1) (2012)
Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
An Easily Testable Routing Architecture and Efficient Test Technique. FPL (2011)
Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A novel reconfigurable logic device base on 3D stack technology. 3DIC (2011)
Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. IEEE Embed. Syst. Lett. 3 (3) (2011)
Shunsuke Oshima, Takuo Nakashima, Toshinori Sueyoshi
Comparison of Properties between Entropy and Chi-Square Based Anomaly Detection Method. NBiS (2011)
Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi
An easily testable routing architecture of FPGA. VLSI-SoC (2011)
Shunsuke Oshima, Takuo Nakashima, Toshinori Sueyoshi
Anomaly Detection Using Chi-square Values Based on the Typical Features and the Time Deviation. AINA (2011)
Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Trans. Electron. (4) (2011)
Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Improving the Soft-error Tolerability of a Soft-core Processor on. J. Next Gener. Inf. Technol. 2 (3) (2011)
Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
Parallelization of the channel width search for FPGA routing. SIGARCH Comput. Archit. News 39 (4) (2011)
Shunsuke Oshima, Yusuke Ichimura, Takuo Nakashima, Toshinori Sueyoshi
An Anomaly Detection System Based on Chi-Square Method with Dynamic BIN Algorithm. BWCCA (2011)
Shunsuke Oshima, Takuo Nakashima, Toshinori Sueyoshi
Early DoS/DDoS Detection Method using Short-term Statistics. CISIS (2010)
Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A robust reconfigurable logic device based on less configuration memory logic cell. FPT (2010)
Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. 4 (1) (2010)
Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. FPL (2010)
Shunsuke Oshima, Takuo Nakashima, Toshinori Sueyoshi
DDoS Detection Technique Using Statistical Analysis to Generate Quick Response Time. BWCCA (2010)
Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Power-aware FPGA routing fabrics and design tools. VLSI-SoC (2010)
Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. FPL (2010)
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM (2010)
Shunsuke Oshima, Arata Hirakawa, Takuo Nakashima, Toshinori Sueyoshi
DoS/DDoS Detection Scheme Using Statistical Method Based on the Destination Port Number. IIH-MSP (2009)
Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
Memory Sharing Approach for TMR Softcore Processor. ARC (2009)
Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi
Improvement of Execution Efficiency on the MX Core. PDCAT (2009)
Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
A novel states recovery technique for the TMR softcore processor. FPL (2009)
Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC (2009)
Takuo Nakashima, Toshinori Sueyoshi
Analysis of Queueing Property for Self-Similar Traffic. AINA (2008)
Takuo Nakashima, Shunsuke Oshima, Yusuke Nishikido, Toshinori Sueyoshi
Extraction of Characteristics of Anomaly Accessed IP Packets by the Entropy-Based Analysis. CISIS (2008)
Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture. Int. J. Reconfigurable Comput. 2008 (2008)
Takuo Nakashima, Akari Ono, Toshinori Sueyoshi
Performance Framework for P2P Overlay Network. IIH-MSP (2008)
Takuo Nakashima, Yusuke Shomura, Toshinori Sueyoshi
Queueing Property for Different Type of Self-Similar Traffics. IIH-MSP (2008)
Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi
A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices. IEICE Trans. Inf. Syst. (12) (2007)
Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi
A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. FPL (2007)
Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. ARC (2007)
Yoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture. FPT (2007)
Takuo Nakashima, Toshinori Sueyoshi
Performance Estimation of TCP under SYN Flood Attacks. CISIS (2007)
Toshinori Sueyoshi
Special Section on Reconfigurable Systems. IEICE Trans. Inf. Syst. (12) (2007)
Takuo Nakashima, Toshinori Sueyoshi
Self-Similar Property for TCP Traffic under the Bottleneck Restrainment. AINA Workshops (1) (2007)
Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM (2007)
Takuo Nakashima, Akari Ono, Toshinori Sueyoshi
Queueing Analysis for Self-similar Traffic by Simulator. IIH-MSP (2007)
Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM (2007)
Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi
Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. VLSI-SoC (2006)
Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi
Effective clustering technique to optimize routability of outer cluster nets. FPGA (2006)
Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi
Applying the Small-World Network to Routing Structure of FPGAs. FPL (2005)
Toshinori Sueyoshi
Foreword. IEICE Trans. Inf. Syst. (8) (2004)
Hidetomo Shibamura, Masayuki Fukuyama, Daisuke Uchida, Seiji Ikeda, Morihiro Kuga, Toshinori Sueyoshi
EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA. FPT (2004)
Toshinori Sueyoshi, Morihiro Kuga, Hidetomo Shibamura
KITE microprocessor and CAE for computer science. Systems and Computers in Japan 33 (8) (2002)
Toshinori Sueyoshi, Masahiro Iida
Configurable and Reconfigurable Computing for Digital Signal Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2002)
Yulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, Toshinori Sueyoshi
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. IEEE Trans. Parallel Distributed Syst. 12 (7) (2001)
Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi
Recursive Diagonal Torus (RDT): An Interconnection Network for the Massively Parallel Computers. Systems and Computers in Japan 27 (9) (1996)
Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN (1994)
Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. SPDP (1993)
Kazuaki J. Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. ICS (1989)
Kazuaki J. Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture. IFIP Congress (1989)
Kazuaki J. Murakami, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
An overview of the Kyushu University reconfigurable parallel processor. SIGARCH Comput. Archit. News 16 (4) (1988)
Toshinori Sueyoshi, Keizo Saisho, Itsujiro Arita
Performance evaluation of the binary tree access mechanism in mimd type parallel computers. Systems and Computers in Japan 17 (9) (1986)
Toshinori Sueyoshi
Hierarchical routing bus. Systems and Computers in Japan 16 (6) (1985)