Qian Zhao

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 26

Top Topics

Software Implementation

Convolutional Neural Network

Hardware Architectures

Top Venues

IEICE Trans. Inf. Syst.

IPSJ Trans. Syst. LSI Des. Methodol.

CANDAR Workshops

Publications

Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida
An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Hui Meng, Qian Zhao, Takaichi Yoshida
A Study of Reconfigurable Switch Architecture for Chiplets Interconnection. CANDARW (2022)
Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Qian Zhao, Masahiro Iida
Reconfigurable Neural Network Accelerator and Simulator for Model Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Longzhen Yu, Qian Zhao, Zhixian Wang
Attention Mechanism Driven YOLOv3 on FPGA Acceleration for Efficient Vision Based Defect Inspection. CSAE (2021)
Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga
Automation of Domain-specific FPGA-IP Generation and Test. HEART (2021)
Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida
A Microcode-based Control Unit for Deep Learning Processors. IPDPS Workshops (2020)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida
Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network. CANDAR (2020)
Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida
A SLM-based overlay architecture for fine-grained virtual FPGA. IEICE Electron. Express 16 (24) (2019)
Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama
A Novel SLM-Based Virtual FPGA Overlay Architecture. MCSoC (2019)
Ryota Watanabe, Yuki Katsuda, Qian Zhao, Takaichi Yoshida
A Pre-Routing Net Wirelength Prediction Method Using an Optimized Convolutional Neural Network. CANDAR Workshops (2019)
Ryota Watanabe, Saika Ura, Qian Zhao, Takaichi Yoshida
Implementation of FPGA Building Platform as a Cloud Service. HEART (2019)
Qian Zhao, Takaichi Yoshida
A Platform-as-a-Service System for FPGA Education and Development. CompEd (2019)
Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida
A Resource Reduced Application-Specific FPGA Switch. ARC (2019)
Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
Three Dimensional FPGA Architecture with Fewer TSVs. IEICE Trans. Inf. Syst. (2) (2018)
Mahdillah Mahdillah, Shinya Nakayama, Qian Zhao, Takaichi Yoshida
An Adaptable Scheduling for Self-Reconfigurable Objects. CANDAR Workshops (2018)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. (2) (2018)
Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT (2017)
Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
A Study of FPGA Virtualization and Accelerator Scheduling. ETCD@ASPLOS (2017)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. 10 (2017)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44 (4) (2016)
Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
hCODE: An open-source platform for FPGA accelerators. FPT (2016)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. (2) (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Simple wafer stacking 3D-FPGA architecture. ICICDT (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. 10 (3) (2015)
Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC (2015)
Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi
A novel three-dimensional FPGA architecture with high-speed serial communication links. FPT (2014)
Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL (2014)
Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC (2013)
Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA (2013)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. (8) (2013)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
An automatic FPGA design and implementation framework. FPL (2013)
Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi
COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Trans. Inf. Syst. (2) (2012)
Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A novel reconfigurable logic device base on 3D stack technology. 3DIC (2011)
Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. IEEE Embed. Syst. Lett. 3 (3) (2011)
Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A robust reconfigurable logic device based on less configuration memory logic cell. FPT (2010)
Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. 4 (1) (2010)