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A robust reconfigurable logic device based on less configuration memory logic cell.
Qian Zhao
Yoshihiro Ichinomiya
Yasuhiro Okamoto
Motoki Amagasaki
Masahiro Iida
Toshinori Sueyoshi
Published in:
FPT (2010)
Keyphrases
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modal logic
neural network
low cost
logic programming
nonmonotonic logics
data structure
knowledge representation
main memory
hardware implementation
multi valued
classical logic
defeasible logic
asynchronous circuits
proof theory
random access memory