Motoki Amagasaki

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 40

Top Topics

Functional Language

Top Venues

IEICE Trans. Inf. Syst.

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Shoki Sakaguchi, Motoki Amagasaki, Masato Kiyama, Toshiaki Okamoto
Multi-Camera People Tracking With Spatio-Temporal and Group Considerations. IEEE Access 12 (2024)
Mery Diana, Masato Kiyama, Motoki Amagasaki, Masayoshi Ito, Yuki Morishita
Advanced Implementation of DNN Translator using ResNet9 for Edge Devices. Int. J. Netw. Comput. 14 (2) (2024)
Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida
An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Mery Diana, Masato Kiyama, Motoki Amagasaki, Masayoshi Ito, Yuki Morishita
A Deep Neural Network Translator for Edge Site Implementation. CANDARW (2023)
Mery Diana, Ridhwan Amin, Motoki Amagasaki, Masato Kiyama
A Lightweight Deep Neural Network Using a Mixer-Type Nonlinear Vector Autoregression. IEEE Access 11 (2023)
Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Qian Zhao, Masahiro Iida
Reconfigurable Neural Network Accelerator and Simulator for Model Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida
A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks. IPSJ Trans. Syst. LSI Des. Methodol. 15 (2022)
Masato Kiyama, Motoki Amagasaki, Masahiro Iida
Development of Quantized DNN Library for Exact Hardware Emulation. CoRR (2021)
Takeyoshi Nagasato, Kei Ishida, Ali Ercan, Tongbi Tu, Masato Kiyama, Motoki Amagasaki, Kazuki Yokoo
Extension of Convolutional Neural Network along Temporal and Vertical Directions for Precipitation Downscaling. CoRR (2021)
Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida
Automatic executable code generation for DNN accelerator ReNA. CANDAR (Workshops) (2021)
Kei Ishida, Ali Ercan, Takeyoshi Nagasato, Masato Kiyama, Motoki Amagasaki
Use of 1D-CNN for input data size reduction of LSTM in Hourly Rainfall-Runoff modeling. CoRR (2021)
Kei Ishida, Masato Kiyama, Ali Ercan, Motoki Amagasaki, Tongbi Tu, Makoto Ueda
Multi-Time-Scale Input Approaches for Hourly-Scale Rainfall-Runoff Modeling based on Recurrent Neural Networks. CoRR (2021)
Kazuki Yokoo, Kei Ishida, Ali Ercan, Tongbi Tu, Takeyoshi Nagasato, Masato Kiyama, Motoki Amagasaki
Capabilities of Deep Learning Models on Learning Physical Relationships: Case of Rainfall-Runoff Modeling with LSTM. CoRR (2021)
Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga
Automation of Domain-specific FPGA-IP Generation and Test. HEART (2021)
Mery Diana, Motoki Amagasaki, Masahiro Iida
Image Search System Based on Feature Vectors of Convolutional Neural Network. TENCON (2020)
Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida
A Microcode-based Control Unit for Deep Learning Processors. IPDPS Workshops (2020)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida
Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network. CANDAR (2020)
Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Masahiro Iida
Relationship between Recognition Accuracy and Numerical Precision in Convolutional Neural Network Models. IEICE Trans. Inf. Syst. (12) (2020)
Motoki Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, Hiroto Ito
R-GCN Based Function Inference for Gate-level Netlist. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida
A SLM-based overlay architecture for fine-grained virtual FPGA. IEICE Electron. Express 16 (24) (2019)
Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama
A Novel SLM-Based Virtual FPGA Overlay Architecture. MCSoC (2019)
Masato Kiyama, Motoki Amagasaki, Masahiro Iida
Deep Learning Framework with Arbitrary Numerical Precision. MCSoC (2019)
Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida
A Quantized Neural Network Library for Proper Implementation of Hardware Emulation. CANDAR Workshops (2019)
Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi
Three Dimensional FPGA Architecture with Fewer TSVs. IEICE Trans. Inf. Syst. (2) (2018)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. (2) (2018)
Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT (2017)
Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. (4) (2017)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. 10 (2017)
Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
High-level Synthesis based on Parallel Design Patterns using a Functional Language. HEART (2017)
Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
FPGA based ASIC Emulator with High Speed Optical Serial Links. HEART (2017)
Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi
An area compact soft error resident circuit for FPGA. ICICDT (2016)
Motoki Amagasaki, Ryo Araki, Masahiro Iida, Toshinori Sueyoshi
SLM: A Scalable Logic Module Architecture with Less Configuration Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44 (4) (2016)
Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
hCODE: An open-source platform for FPGA accelerators. FPT (2016)
Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi
A novel soft error tolerant FPGA architecture. VLSI-SoC (2016)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. (2) (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Simple wafer stacking 3D-FPGA architecture. ICICDT (2015)
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. 10 (3) (2015)
Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC (2015)
Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi
A novel three-dimensional FPGA architecture with high-speed serial communication links. FPT (2014)
Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Blokus Duo engine on a Zynq. FPT (2014)
Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Zyndroid: An Android platform for software/hardware coprocessing. FPT (2014)
Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL (2014)
Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC (2013)
Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA (2013)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. (8) (2013)
Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
A reconfigurable Java accelerator with software compatibility for embedded systems. SIGARCH Comput. Archit. News 41 (5) (2013)
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
An automatic FPGA design and implementation framework. FPL (2013)
Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. ICA3PP (1) (2012)
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel physical defects recovery technique for FPGA-IP cores. ReConFig (2012)
Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. FPT (2012)
Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. FCCM (2012)
Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi
COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Trans. Inf. Syst. (2) (2012)
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC (2012)
Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
An Easily Testable Routing Architecture and Prototype Chip. IEICE Trans. Inf. Syst. (2) (2012)
Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Fault detection and avoidance of FPGA in various granularities. FPL (2012)
Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. ICA3PP (1) (2012)
Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
An Easily Testable Routing Architecture and Efficient Test Technique. FPL (2011)
Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A novel reconfigurable logic device base on 3D stack technology. 3DIC (2011)
Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. IEEE Embed. Syst. Lett. 3 (3) (2011)
Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi
An easily testable routing architecture of FPGA. VLSI-SoC (2011)
Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Trans. Electron. (4) (2011)
Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Improving the Soft-error Tolerability of a Soft-core Processor on. J. Next Gener. Inf. Technol. 2 (3) (2011)
Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
Parallelization of the channel width search for FPGA routing. SIGARCH Comput. Archit. News 39 (4) (2011)
Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A robust reconfigurable logic device based on less configuration memory logic cell. FPT (2010)
Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. 4 (1) (2010)
Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. FPL (2010)
Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Power-aware FPGA routing fabrics and design tools. VLSI-SoC (2010)
Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. FPL (2010)
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM (2010)
Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
Memory Sharing Approach for TMR Softcore Processor. ARC (2009)
Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
A novel states recovery technique for the TMR softcore processor. FPL (2009)
Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC (2009)
Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture. Int. J. Reconfigurable Comput. 2008 (2008)
Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi
A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. FPL (2007)
Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. ARC (2007)
Yoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi
An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture. FPT (2007)
Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi
Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. VLSI-SoC (2006)