An area compact soft error resident circuit for FPGA.
Motoki AmagasakiYuji NakamuraTakuya TeraokaMasahiro IidaToshinori SueyoshiPublished in: ICICDT (2016)
Keyphrases
- high speed
- power reduction
- error bounds
- real time
- circuit design
- low cost
- signal processing
- error rate
- hardware implementation
- real time image processing
- data sets
- parallel hardware
- error detection
- field programmable gate array
- neural network
- error analysis
- hardware design
- smart home
- electronic circuits
- video sequences