Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration.
Makoto FujinoHiroki TanakaYoshihiro IchinomiyaMotoki AmagasakiMorihiro KugaMasahiro IidaToshinori SueyoshiPublished in: ICA3PP (1) (2012)
Keyphrases
- hardware architecture
- error detection
- field programmable gate array
- normal operation
- fault isolation
- fault detection
- fault diagnosis
- high speed
- error correction
- hardware implementation
- recovery algorithm
- manufacturing systems
- instruction set
- parallel computing
- expert systems
- database systems
- processor core
- multiprocessor systems
- distributed memory
- computer architecture
- low cost
- fuzzy logic