An Easily Testable Routing Architecture and Prototype Chip.
Kazuki InoueMasahiro KogaMotoki AmagasakiMasahiro IidaYoshinobu IchidaMitsuro SajiJun IidaToshinori SueyoshiPublished in: IEICE Trans. Inf. Syst. (2012)
Keyphrases
- vlsi implementation
- high speed
- low cost
- analog vlsi
- packet switching
- single chip
- modular architecture
- software architecture
- routing algorithm
- network topology
- high density
- database
- memory access
- cmos technology
- routing protocol
- network on chip
- cmos image sensor
- real time
- network infrastructure
- management system
- middleware architecture