Kazuki Inoue

Publication Activity (10 Years)

Years Active: 2009-2018
Publications (10 Years): 3

Top Topics

Patent Information

Hardware Design

Intellectual Property

Fault Detection

Top Venues

IEICE Trans. Inf. Syst.

Publications

Ryota Natsume, Kazuki Inoue, Yoshihiro Fukuhara, Shintaro Yamamoto, Shigeo Morishima, Hirokatsu Kataoka
Understanding Fake Faces. ECCV Workshops (3) (2018)
Ryota Natsume, Kazuki Inoue, Yoshihiro Fukuhara, Shintaro Yamamoto, Shigeo Morishima, Hirokatsu Kataoka
Understanding Fake Faces. CoRR (2018)
Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. (4) (2017)
Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA (2013)
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. (8) (2013)
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
A novel physical defects recovery technique for FPGA-IP cores. ReConFig (2012)
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC (2012)
Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
An Easily Testable Routing Architecture and Prototype Chip. IEICE Trans. Inf. Syst. (2) (2012)
Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Fault detection and avoidance of FPGA in various granularities. FPL (2012)
Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
An Easily Testable Routing Architecture and Efficient Test Technique. FPL (2011)
Masahiro Toba, Yuji Hayashi, Koji Murai, Kazuki Inoue
Evaluation of human distress by one's walking speed - toward development of early warning system for marine pilots' condition. SoSE (2011)
Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi
An easily testable routing architecture of FPGA. VLSI-SoC (2011)
Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Trans. Electron. (4) (2011)
Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. 4 (1) (2010)
Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC (2009)