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A novel physical defects recovery technique for FPGA-IP cores.
Yuki Nishitani
Kazuki Inoue
Motoki Amagasaki
Masahiro Iida
Morihiro Kuga
Toshinori Sueyoshi
Published in:
ReConFig (2012)
Keyphrases
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high speed
signal processing
hardware implementation
field programmable gate array
real time
low cost
real time image processing
wdm networks
physical world
hardware design
single chip
image recovery
fpga implementation
recovery algorithm
printed circuit boards
parallel hardware
hardware architecture
neural network