Architecture exploration of 3D FPGA to minimize internal layer connection.
Motoki AmagasakiYuto TakeuchiQian ZhaoMasahiro IidaMorihiro KugaToshinori SueyoshiPublished in: VLSI-SoC (2015)
Keyphrases
- hardware architecture
- multi layer
- hardware implementation
- hardware design
- fpga implementation
- high speed
- field programmable gate array
- real time
- fpga technology
- hierarchical architecture
- management system
- systolic array
- dedicated hardware
- software implementation
- software architecture
- hardware architectures
- pipelined architecture
- data flow
- network architecture
- single chip
- architectural design
- internal and external
- image processing algorithms
- efficient implementation
- signal processing
- low cost
- general purpose processors
- abstraction layer
- image processing