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Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration.

Yoshihiro IchinomiyaShiro TanoueMotoki AmagasakiMasahiro IidaMorihiro KugaToshinori Sueyoshi
Published in: FCCM (2010)
Keyphrases
  • hardware architecture
  • field programmable gate array
  • high speed
  • computational efficiency
  • database
  • high robustness
  • feature extraction
  • parallel processing