Login / Signup
A novel states recovery technique for the TMR softcore processor.
Shiro Tanoue
Tomoyuki Ishida
Yoshihiro Ichinomiya
Motoki Amagasaki
Morihiro Kuga
Toshinori Sueyoshi
Published in:
FPL (2009)
Keyphrases
</>
hardware architecture
field programmable gate array
error detection
hardware implementation
high speed
computer architecture
image processing
parallel processing
recovery algorithm
error correction
image processing algorithms
high end
single chip
parallel architecture
image recovery