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IPSJ Trans. Syst. LSI Des. Methodol.
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2008
2023
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Publications
volume 16, 2023
Tamon Sadasue
,
Tsuyoshi Isshiki
LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure.
IPSJ Trans. Syst. LSI Des. Methodol.
16 (2023)
Atsushi Takahashi
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
16 (2023)
Gaku Kataoka
,
Masahiro Yamamoto
,
Masato Inagi
,
Shinobu Nagayama
,
Shin'ichi Wakabayashi
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection.
IPSJ Trans. Syst. LSI Des. Methodol.
16 (2023)
Kiyoharu Hamaguchi
Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage.
IPSJ Trans. Syst. LSI Des. Methodol.
16 (2023)
Kotaro Shimamura
,
Takeshi Takehara
,
Naohiro Ikeda
Measurement Results of Real Circuit Delay Degradation under Realistic Workload.
IPSJ Trans. Syst. LSI Des. Methodol.
16 (2023)
Ippei Tanaka
,
Naoyuki Miyagawa
,
Tomoya Kimura
,
Takashi Imagawa
,
Hiroyuki Ochi
A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor.
IPSJ Trans. Syst. LSI Des. Methodol.
16 (2023)
volume 15, 2022
Atsushi Takahashi
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
15 (2022)
Yasuhiro Nakahara
,
Yuta Masuda
,
Masato Kiyama
,
Motoki Amagasaki
,
Masahiro Iida
A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks.
IPSJ Trans. Syst. LSI Des. Methodol.
15 (2022)
Mingfei Yu
,
Yukio Miyasaka
,
Masahiro Fujita
Parallel Scheduling Attention Mechanism: Generalization and Optimization.
IPSJ Trans. Syst. LSI Des. Methodol.
15 (2022)
volume 14, 2021
Tamon Sadasue
,
Takuya Tanaka
,
Ryosuke Kasahara
,
Arief Darmawan
,
Tsuyoshi Isshiki
Scalable Hardware Architecture for fast Gradient Boosted Tree Training.
IPSJ Trans. Syst. LSI Des. Methodol.
14 (2021)
Youngsoo Shin
Computational Lithography Using Machine Learning Models.
IPSJ Trans. Syst. LSI Des. Methodol.
14 (2021)
Yosuke Mukasa
,
Shu Tanaka
,
Nozomu Togawa
Experimental Evaluations of Parallel Tempering on an Ising Machine.
IPSJ Trans. Syst. LSI Des. Methodol.
14 (2021)
Satoshi Ito
,
Hiroki Nishikawa
,
Xiangbo Kong
,
Yusuke Funabashi
,
Atsuya Shibata
,
Shunsuke Negoro
,
Ittetsu Taniguchi
,
Hiroyuki Tomiyama
Energy-aware Routing of Delivery Drones under Windy Conditions.
IPSJ Trans. Syst. LSI Des. Methodol.
14 (2021)
Atsushi Takahashi
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
14 (2021)
Shinichi Nishizawa
,
Shih-Ting Lin
,
Yih-Lang Li
,
Hidetoshi Onodera
Supplemental PDK for ASAP7 Using Synopsys Flow.
IPSJ Trans. Syst. LSI Des. Methodol.
14 (2021)
Qiaochu Zhao
,
Ittetsu Taniguchi
,
Takao Onoye
A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System.
IPSJ Trans. Syst. LSI Des. Methodol.
14 (2021)
volume 13, 2020
Motoki Amagasaki
,
Hiroki Oyama
,
Yuichiro Fujishiro
,
Masahiro Iida
,
Hiroaki Yasuda
,
Hiroto Ito
R-GCN Based Function Inference for Gate-level Netlist.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Yukio Mitsuyama
,
Takashi Asada
,
Makio Eguchi
Measurement of Variations in FPGAs under Various Load Conditions.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Atsushi Takahashi
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Peikun Wang
,
Amir Masoud Gharehbaghi
,
Masahiro Fujita
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Kenshu Seto
Shift Register Initialization in Scalar Replacement for Reducing Code Size.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Yusuke Funabashi
,
Atsuya Shibata
,
Shunsuke Negoro
,
Ittetsu Taniguchi
,
Hiroyuki Tomiyama
A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Ryota Ishikawa
,
Masashi Tawada
,
Masao Yanagisawa
,
Nozomu Togawa
Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Sheldon X.-D. Tan
,
Zeyu Sun
,
Sheriff Sadiqbatcha
Interconnect Electromigration Modeling and Analysis for Nanometer ICs: From Physics to Full-Chip.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Yukio Miyasaka
,
Akihiro Goda
,
Ashish Mittal
,
Masahiro Fujita
Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Takumi Hosaka
,
Shinichi Nishizawa
,
Ryo Kishida
,
Takashi Matsumoto
,
Kazutoshi Kobayashi
Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
Kotaro Shimamura
,
Naohiro Ikeda
Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator.
IPSJ Trans. Syst. LSI Des. Methodol.
13 (2020)
volume 12, 2019
Seiya Shirakuni
,
Ittetsu Taniguchi
,
Hiroyuki Tomiyama
Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Hiroki Koyasu
,
Yasuhiro Takahashi
Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
A. K. M. Mahfuzul Islam
,
Hidetoshi Onodera
Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Salita Sombatsiri
,
Seiya Shibata
,
Yuki Kobayashi
,
Hiroaki Inoue
,
Takashi Takenaka
,
Takeo Hosomi
,
Jaehoon Yu
,
Yoshinori Takeuchi
Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Kenshu Seto
Scalar Replacement with Circular Buffers.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Nobutaka Kito
,
Kazuyoshi Takagi
,
Naofumi Takagi
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Nozomu Togawa
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Takafumi Miyazaki
,
Shunsuke Takai
,
Ittetsu Taniguchi
,
Hiroyuki Tomiyama
An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture on Zynq-7000 SoC.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Chaofei Yang
,
Ximing Qiao
,
Yiran Chen
Neuromorphic Computing Systems: From CMOS To Emerging Nonvolatile Memory.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Yang Liu
,
Lin Meng
,
Hiroyuki Tomiyama
A Genetic Algorithm for Scheduling of Data-parallel Tasks on Multicore Architectures.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Koichi Fujiwara
,
Kazushi Kawamura
,
Masao Yanagisawa
,
Nozomu Togawa
An FPGA Implementation Method based on Distributed-register Architectures.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
Kana Shimada
,
Ittetsu Taniguchi
,
Hiroyuki Tomiyama
Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures.
IPSJ Trans. Syst. LSI Des. Methodol.
12 (2019)
volume 11, 2018
Nozomu Togawa
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
11 (2018)
Kenshu Seto
Scalar Replacement with Polyhedral Model.
IPSJ Trans. Syst. LSI Des. Methodol.
11 (2018)
Melanie Diepenbeck
,
Ulrich Kühne
,
Mathias Soeken
,
Daniel Große
,
Rolf Drechsler
Behaviour Driven Development for Hardware Design.
IPSJ Trans. Syst. LSI Des. Methodol.
11 (2018)
Daisuke Oku
,
Masao Yanagisawa
,
Nozomu Togawa
Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures.
IPSJ Trans. Syst. LSI Des. Methodol.
11 (2018)
Bing Li
,
Masanori Hashimoto
,
Ulf Schlichtmann
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era.
IPSJ Trans. Syst. LSI Des. Methodol.
11 (2018)
volume 10, 2017
Qian Zhao
,
Motoki Amagasaki
,
Masahiro Iida
,
Morihiro Kuga
,
Toshinori Sueyoshi
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost.
IPSJ Trans. Syst. LSI Des. Methodol.
10 (2017)
Ahmed Awad
,
Atsushi Takahashi
,
Satoshi Tanaka
,
Chikaaki Kodama
Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement.
IPSJ Trans. Syst. LSI Des. Methodol.
10 (2017)
Yusuke Matsunaga
An Accelerating Technique for SAT-based ATPG.
IPSJ Trans. Syst. LSI Des. Methodol.
10 (2017)
Nozomu Togawa
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol.
10 (2017)
Farhan Shafiq
,
Tsuyoshi Isshiki
,
Dongju Li
An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters.
IPSJ Trans. Syst. LSI Des. Methodol.
10 (2017)
Johann Knechtel
,
Ozgur Sinanoglu
,
Ibrahim Abe M. Elfadel
,
Jens Lienig
,
Cliff C. N. Sze
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration.
IPSJ Trans. Syst. LSI Des. Methodol.
10 (2017)