Tohru Ishihara

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 46

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

ASP-DAC

ISQED

SoCC

Publications

Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (3) (2024)
Takumi Komori, Yutaka Masuda, Tohru Ishihara
Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (1) (2024)
Tohru Ishihara
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 17 (2024)
Yutaka Masuda, Yusei Honda, Tohru Ishihara
Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Yusei Honda, Yutaka Masuda, Tohru Ishihara
Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. IOLTS (2023)
Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. DATE (2023)
Lingxiao Hou, Yutaka Masuda, Tohru Ishihara
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. SOCC (2023)
Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. ISVLSI (2022)
Lingxiao Hou, Yutaka Masuda, Tohru Ishihara
An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. ASP-DAC (2022)
Akihiko Shinya, Kengo Nozaki, Shota Kita, Tohru Ishihara, Shinji Matsuo, Masaya Notomi
Energy efficient OEO conversion and its applications to photonic integrated systems. OFC (2022)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC (2022)
Takumi Komori, Yutaka Masuda, Tohru Ishihara
DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. RTCSA (2022)
Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. DAC (2022)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE (2021)
Kazuki Yoshisue, Yutaka Masuda, Tohru Ishihara
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. IOLTS (2021)
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2021)
Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED (2021)
Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2021)
Khyati Kiyawat, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI (2020)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. ICRC (2020)
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. ISVLSI (2020)
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. ASP-DAC (2019)
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC (2019)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. Integr. 65 (2019)
Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
A Design Method of a Cell-Based Amplifier for Body Bias Generation. IEICE Trans. Electron. (7) (2019)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. ICRC (2018)
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. PATMOS (2018)
Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera
Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. IOLTS (2018)
Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics. ICRC (2018)
Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. SoCC (2018)
Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
Minimum Energy Point Tracking with All-Digital On-Chip Sensors. J. Low Power Electron. 14 (2) (2018)
Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi
An Integrated Nanophotonic Parallel Adder. ACM J. Emerg. Technol. Comput. Syst. 14 (2) (2018)
Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera
On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator. VLSI-DAT (2017)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. PATMOS (2016)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Variability- and correlation-aware logical effort for near-threshold circuit design. ISQED (2016)
Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi
An integrated optical parallel adder as a first step towards light speed data processing. ISOCC (2016)
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing. SoCC (2016)
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. ASP-DAC (2016)
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Microarchitectural-level statistical timing models for near-threshold circuit design. ASP-DAC (2015)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. IEEE J. Solid State Circuits 50 (11) (2015)
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
An energy-efficient on-chip memory structure for variability-aware near-threshold operation. ISQED (2015)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
An impact of process variation on supply voltage dependence of logic path delay variation. VLSI-DAT (2015)
Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
Energy reduction by built-in body biasing with single supply voltage operation. ISQED (2015)
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Variation-aware Flip-Flop energy optimization for ultra low voltage operation. SoCC (2014)
Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. A-SSCC (2014)
Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada
An Integrated Framework for Energy Optimization of Embedded Real-Time Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. SoCC (2014)
Ji Gu, Hui Guo, Tohru Ishihara
DLIC: Decoded loop instructions caching for energy-aware embedded processors. ACM Trans. Embed. Comput. Syst. 13 (1) (2013)
Kyungsoo Lee, Tohru Ishihara
DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Analysis and comparison of XOR cell structures for low voltage circuit design. ISQED (2013)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Ji Gu, Tohru Ishihara
A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems. SMARTGREENS (2012)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
A flexible structure of standard cell and its optimization method for near-threshold voltage operation. ICCD (2012)
Ji Gu, Tohru Ishihara, Kyungsoo Lee
Loop instruction caching for energy-efficient embedded multitasking processors. ESTIMedia (2012)
Kyungsoo Lee, Tohru Ishihara
A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems. SMARTGREENS (2012)
Lovic Gauthier, Tohru Ishihara
Processor Energy Characterization for Compiler-Assisted Software Energy Reduction. J. Electr. Comput. Eng. 2012 (2012)
Kyungsoo Lee, Tohru Ishihara
I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays. ESTIMedia (2012)
Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
A Standard Cell Optimization Method for Near-Threshold Voltage Operations. PATMOS (2012)
Takumi Okuhira, Tohru Ishihara
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. PATMOS (2011)
Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada
An integrated optimization framework for reducing the energy consumption of embedded real-time applications. ISLPED (2011)
Maziar Goudarzi, Tohru Ishihara, Hamid Noori
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies. Trans. High Perform. Embed. Archit. Compil. 3 (2011)
Akitoshi Matsuda, Tohru Ishihara
Developing an integrated verification and debug methodology. DATE (2011)
Lovic Gauthier, Tohru Ishihara
Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada
Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. CASES (2010)
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. J. Signal Process. Syst. 60 (2) (2010)
Tohru Ishihara
A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Maziar Goudarzi, Tohru Ishihara
SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation. IEEE Trans. Very Large Scale Integr. Syst. 18 (12) (2010)
Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura
An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP (2010)
Lovic Gauthier, Tohru Ishihara
Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories. ESTIMedia (2009)
Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
An Optimization Technique for Low-Energy Embedded Memory Systems. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. ISVLSI (2008)
Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Tohru Ishihara
A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. EUC (1) (2008)
Maziar Goudarzi, Tohru Ishihara
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. ISLPED (2008)
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
variation. Microelectron. J. 39 (12) (2008)
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI (2008)
Maziar Goudarzi, Tohru Ishihara
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. ACM Great Lakes Symposium on VLSI (2008)
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Trans. Electron. (4) (2008)
Maziar Goudarzi, Tohru Ishihara
Value-dependence of SRAM leakage in deca-nanometer technologies. IEICE Electron. Express 5 (1) (2008)
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS (2008)
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
Way-Scaling to Reduce Power of Cache with Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP (2008)
Maziar Goudarzi, Tohru Ishihara, Hamid Noori
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. HiPEAC (2008)
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTIMedia (2007)
Tohru Ishihara, Farzan Fallah
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors CoRR (2007)
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
Task scheduling for reliable cache architectures of multiprocessor systems. DATE (2007)
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC (2007)
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Trans. Electron. (10) (2007)
Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah
An Energy Characterization Framework for Software-Based Embedded Systems. ESTIMedia (2006)
Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto
A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Tohru Ishihara