Shinichi Nishizawa

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 30

Top Topics

Convolutional Neural Networks

Design Methodology

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IPSJ Trans. Syst. LSI Des. Methodol.

Microelectron. Reliab.

Publications

Thatree Mamee, Zaiqi Lou, Katsuhiro Hata, Makoto Takamiya, Takayasu Sakurai, Shinichi Nishizawa, Wataru Saito
Estimating of IGBT Bond Wire Lift-Off Trend Using Convolutional Neural Network (CNN). IEEE Access 12 (2024)
Zekun Wang, Shinichi Nishizawa, Shinji Kimura
An 8-point Approximate DCT Design with Optimized Signed Digit Encoding. SOCC (2023)
Zaiqi Lou, Thatree Mamee, Katsuhiro Hata, Makoto Takamiya, Shinichi Nishizawa, Wataru Saito
IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control. IEEE Access 11 (2023)
Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura
Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction. SOCC (2023)
Shinichi Nishizawa, Toru Nakura
Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura
Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks. SOCC (2023)
Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura
Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 70 (5) (2023)
Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura
A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery. SOCC (2023)
Shinichi Nishizawa, Toru Nakura
Density Aware Cell Library Design for Design-Technology Co-Optimization. ISQED (2022)
Yuki Imai, Shinichi Nishizawa, Kazuhito Ito
Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera
Supplemental PDK for ASAP7 Using Synopsys Flow. IPSJ Trans. Syst. LSI Des. Methodol. 14 (2021)
Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi
Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. ICCAD (2020)
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. DAC (2019)
Mahfuzul Islam, Shinichi Nishizawa, Yusuke Matsui, Yoshinobu Ichida
Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits. ISQED (2019)
Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito
Analog circuit design methodology utilizing a structure of thin BOX FDSOI. IEICE Electron. Express 16 (5) (2019)
Toshiro Hiramoto, K. Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, T. Sarava, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, H. Ohashi, K. Itou, T. Takakura, M. Fukui, S. Suzuki, Ken Takeuchi, Masanori Tsukuda, Y. Numasawa
Switching of 3300V Scaled IGBT by 5V Gate Drive. ASICON (2019)
Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi
Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement. IOLTS (2019)
Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa
Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Shinichi Nishizawa, Hidetoshi Onodera
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Kazunori Hasegawa, Shinichi Nishizawa, Ichiro Omura
ESR and capacitance monitoring of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier. Microelectron. Reliab. (2018)
Shinichi Nishizawa, Hidetoshi Onodera
Process variation aware D-Flip-Flop design using regression analysis. ISQED (2018)
Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, H. Ohashi, Hiroshi Iwai
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits (2018)
Kazunori Hasegawa, K. Tsuzaki, Shinichi Nishizawa
DC-bias-voltage dependence of degradation of aluminum electrolytic capacitors. Microelectron. Reliab. 83 (2018)
Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately. ESSDERC (2018)
Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC (2017)
Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, H. Ohashi, Hiroshi Iwai
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). ASICON (2017)
Kazunori Hasegawa, Ichiro Omura, Shinichi Nishizawa
Design and Analysis of a New Evaluation Circuit for Capacitors Used in a High-Power Three-Phase Inverter. IEEE Trans. Ind. Electron. 63 (5) (2016)
Kazunori Hasegawa, K. Kozuma, K. Tsuzaki, Ichiro Omura, Shinichi Nishizawa
Temperature rise measurement for power-loss comparison of an aluminum electrolytic capacitor between sinusoidal and square-wave current injections. Microelectron. Reliab. 64 (2016)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
An impact of process variation on supply voltage dependence of logic path delay variation. VLSI-DAT (2015)
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Variation-aware Flip-Flop energy optimization for ultra low voltage operation. SoCC (2014)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. SoCC (2014)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Analysis and comparison of XOR cell structures for low voltage circuit design. ISQED (2013)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
A flexible structure of standard cell and its optimization method for near-threshold voltage operation. ICCD (2012)
Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
A Standard Cell Optimization Method for Near-Threshold Voltage Operations. PATMOS (2012)
Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation. ISQED (2011)
Taiki Hashizume, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui
An Efficient Hardware Accelerator for Power Grid Simulation. ISCAS (2009)