Masaya Yoshikawa

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 45

Top Topics

Evaluation Method

Top Venues

Publications

Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
Explainable AI based Adversarial Examples and its Evaluation. ICECC (2023)
Masato Sato, Yusuke Nozaki, Masaya Yoshikawa
Implementation and Evaluation of the Lightweight Cipher SPARKLE. ICECC (2023)
Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa
Machine Learning Based Power Analysis for Simon with Secure Mechanism. ICCAE (2023)
Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa
Security Evaluation of Glitch Based Authentication Function for Edge AI. GCCE (2023)
Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa
Hamming Weight aware Fault Analysis for Lightweight Cryptography TWINE. CCIOT (2023)
Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa
Deep Learning Based Side-Channel Analysis for Lightweight Cipher PRESENT. ICCAE (2023)
Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa
Tamper Resistance Evaluation of Midori128 against Differential Power Analysis. ICKII (2023)
Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa
AI Hardware Oriented Trojan Detection Architecture. ICECC (2022)
Daichi Hirose, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
Authenticated Encryption based Secure In-vehicle System against DoS Attacks. GCCE (2022)
Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa
Hardware Trojan for Lightweight Cryptoraphy Elephant. GCCE (2021)
Yusuke Nozaki, Masaya Yoshikawa
Neural Network Based Glitch Physically Unclonable Function. UEMCON (2021)
Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa
Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7. ISDCS (2021)
Yusuke Nozaki, Masaya Yoshikawa
Tamper Resistance Evaluation of TWINE Implemented on 8-bit Microcontroller. ICSIM (2020)
Yusuke Nozaki, Masaya Yoshikawa
Unrolled PRINCE Cipher based Glitch Physically Unclonable Function. ICISS (2020)
Yusuke Nozaki, Masaya Yoshikawa
Side-Channel Resistance Evaluation Method using Statistical Tests for Physical Unclonable Function. ICAIIC (2019)
Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa
Security Evaluation of Counter Synchronization Method for CAN Against DoS Attack. GCCE (2019)
Yusuke Nozaki, Masaya Yoshikawa
Security Evaluation of Ring Oscillator PUF Against Genetic Algorithm Based Modeling Attack. IMIS (2019)
Yusuke Nozaki, Masaya Yoshikawa
Quantitative Performance Evaluation of PL PUF and RO PUF with ASIC Implementation. GCCE (2019)
Taichi Umeda, Yusuke Nozaki, Masaya Yoshikawa
Scalability and Performance Evaluation of GA Based Modeling Analysis for RO PUF. GCCE (2019)
Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
Evaluation of the Hiding-Countermeasure PRINCE Using Differential Power Analysis. GCCE (2019)
Yusuke Nozaki, Masaya Yoshikawa
Secret Sharing Schemes Based Secure Authentication for Physical Unclonable Function. ICCCS (2019)
Yusuke Nozaki, Masaya Yoshikawa
Countermeasure of Lightweight Physical Unclonable Function Against Side-Channel Attack. CCC (2019)
Masaya Yoshikawa, Yusuke Nozaki
Side-Channel Analysis for Searchable Encryption System and its Security Evaluation. CSE/EUC (2019)
Shu Takemoto, Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa, Shinya Honda, Ryo Kurachi
Performance Evaluation of CAESAR Authenticated Encryption on SROS2. AICCC (2019)
Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa
Statistical Power Analysis for IoT Device Oriented Encryption with Glitch Canceller. IWCIA (2019)
Yusuke Nozaki, Masaya Yoshikawa
EM based machine learning attack for XOR arbiter PUF. ICMLSC (2018)
Yusuke Nozaki, Masaya Yoshikawa
Shuffling Based Side-Channel Countermeasure for Energy Harvester. GCCE (2018)
Yusuke Nozaki, Masaya Yoshikawa
Security Evaluation of a Lightweight Cipher SPECK against Round Addition DFA. AICCC (2018)
Taichi Umeda, Kazuya Shibagaki, Yusuke Nozaki, Masaya Yoshikawa
Lethal Genes Aware Genetic Programming Analysis for RO PUF. GCCE (2018)
Kazuya Shibagaki, Taichi Umeda, Yusuke Nozaki, Masaya Yoshikawa
Feasibility Evaluation of Neural Network Physical Unclonable Function. GCCE (2018)
Masaya Yoshikawa, Yoshiya Ikezaki, Yusuke Nozaki
Implementation of Searchable Encryption System with Dedicated Hardware and its Evaluation. UEMCON (2018)
Masaya Yoshikawa, Yusuke Nozaki
Lightweight Cipher Aware Countermeasure Using Random Number Masks and Its Evaluation. ICVISP (2018)
Susumu Matsumi, Yusuke Nozaki, Masaya Yoshikawa
Feature Extraction Driven Modeling Attack Against Double Arbiter PUF and Its Evaluation. AICCC (2018)
Masaya Yoshikawa, Yusuke Nozaki
Helper Data Aware Cloning Method for Physical Unclonable Function. SmartCloud (2017)
Masaya Yoshikawa, Yusuke Nozaki
Electromagnetic analysis method for ultra low power cipher Midori. UEMCON (2017)
Yoshiya Ikezaki, Yusuke Nozaki, Hideki Nagata, Masaya Yoshikawa
FPGA implementation technique for power consumption aware tamper resistance accelerator of lightweight PUF. GCCE (2017)
Yusuke Nozaki, Yoshiya Ikezaki, Hideki Nagata, Masaya Yoshikawa
Power analysis for a lightweight authenticated encryption SIMON-JAMBU. GCCE (2017)
Yusuke Nozaki, Masaya Yoshikawa
Tamper resistance evaluation of PUF implementation against machine learning attack. ICBEA (2017)
Masaya Yoshikawa, Yusuke Nozaki
Hierarchical power analysis attack for falsification detection cipher. CCWC (2017)
Yusuke Nozaki, Masaya Yoshikawa
Statistical fault analysis for a lightweight cipher midori. ICIA (2017)
Masaya Yoshikawa, Yusuke Nozaki
Two Stage Fault Analysis against a Falsification Detection Cipher Minalpher. SmartCloud (2016)
Masaya Yoshikawa, Yusuke Nozaki, Kensaku Asahi
Vulnerability Evaluation Accelerator for Lightweight Ciphers. BigDataSecurity/HPSC/IDS (2016)
Masaya Yoshikawa, Yusuke Nozaki, Kensaku Asahi
Multiple Rounds Aware Power Analysis Attack for a Lightweight Cipher SIMECK. BigDataService (2016)
Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa
Deep learning attack for physical unclonable function. GCCE (2016)
Yusuke Nozaki, Yoshiya Ikezaki, Masaya Yoshikawa
Hardware Trojan for an authenticated encryption Minalpher. GCCE (2016)
Masaya Yoshikawa, Kyota Sugioka, Yusuke Nozaki, Kensaku Asahi
Secure in-vehicle systems against Trojan attacks. ICIS (2015)
Masaya Yoshikawa, Yusuke Nozaki, Toshiya Asai, Kensaku Asahi
Frequency Domain Aware Power Analysis Attack against Random Clock LSI for Secure Automotive Embedded Systems. VTC Fall (2015)
Takato Iwase, Yusuke Nozaki, Masaya Yoshikawa, Takeshi Kumaki
Detection technique for hardware Trojans using machine learning in frequency domain. GCCE (2015)
Kohei Nohara, Yusuke Nozaki, Masaya Yoshikawa
Hardware Trojan for ultra lightweight block cipher Piccolo. GCCE (2015)
Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa
Statistical fault analysis for a lightweight block cipher TWINE. GCCE (2015)
Masaya Yoshikawa, Kyota Sugioka, Yusuke Nozaki, Kensaku Asahi
Secure in-vehicle Systems using Authentication. Int. J. Networked Distributed Comput. 3 (3) (2015)
Masaya Yoshikawa, Takuya Tsukadaira, Takeshi Kumaki
Design and LSI prototyping of security module with hardware trojan. ICCE (2015)
Yusuke Nozaki, Toshiya Asai, Kensaku Asahi, Masaya Yoshikawa
Power analysis for clock fluctuation LSI. SNPD (2015)
Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa
PUF ID generation method for modeling attacks. GCCE (2014)
S. Kiryu, Kensaku Asahi, Masaya Yoshikawa
Vulnerability evaluation of multiplexing PUF for SVM attacks. ICSEng (2014)
Masaya Yoshikawa, Hikaru Goto, Kensaku Asahi
Error value driven fault analysis attack. SNPD (2014)
Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino
Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2014)
Kohei Nohara, Kensaku Asahi, Masaya Yoshikawa
Study of threat for automotive embedded system by Trojan virus. GCCE (2014)
Masaya Yoshikawa, R. Satoh, Takeshi Kumaki
Hardware Trojan for security LSI. ICCE (2013)
Masaya Yoshikawa, Toshiya Asai
Platform for Verification of Electromagnetic Analysis Attacks against Cryptographic Circuits. ITNG (2013)
Takeshi Kumaki, Masaya Yoshikawa, Takeshi Fujino
Cipher-destroying and secret-key-emitting hardware Trojan against AES core. MWSCAS (2013)
Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino
The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. VLSI-DAT (2013)
Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino
Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Trans. Electron. (4) (2012)
Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka, Masaya Yoshikawa, Takeshi Fujino
Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2012)
Masaya Yoshikawa, Akira Naruse
Multiplexing aware arbiter physical unclonable function. IRI (2012)
Masaya Yoshikawa, M. Sugiyama
Multi-rounds masking method against DPA attacks. IRI (2011)
Masaya Yoshikawa, Takeshi Fujino
Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. Int. J. Comput. Their Appl. 18 (4) (2011)
Masaya Yoshikawa, Y. Kojima
Efficient Random Number for the Masking Method against DPA Attacks. ICSEng (2011)
Masahiro Fukui, Haruo Miki, Masaya Yoshikawa, Shuji Tsukiyama
A power grid optimization algorithm considering via reliability. ECCTD (2011)
Masaya Yoshikawa, Shimohigashi Yoshiaki
Hybrid Ant Colony Optimization for intensification and diversification. IRI (2010)
Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino
Placement Tool Dedicated for a Via-programmable Logic Device VPEX. CAINE (2010)
Masaya Yoshikawa, Akira Naruse, Shinsuke Souboku
Adaptive Immune Algorithm Considering Intensification and Diversification. IRI (2009)
Masaya Yoshikawa, Hidekazu Terai
OX Hardware Engine for High Speed Character Inheritance. GEM (2009)
Taiki Hashizume, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui
An Efficient Hardware Accelerator for Power Grid Simulation. ISCAS (2009)
Masaya Yoshikawa, Hidekazu Terai
Dedicated Hardware for Ant Colony Optimization Using Distributed Memory. ITNG (2009)
Masaya Yoshikawa, Hidekazu Terai
Car Navigation System Based on Hybrid Genetic Algorithm. CSIE (5) (2009)
Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino
Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. IEICE Trans. Electron. (4) (2008)
Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai
Hybrid Architecture of Genetic Algorithm and Simulated Annealing. Eng. Lett. 16 (3) (2008)
Masaya Yoshikawa, Hidekazu Terai
Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization. GEM (2008)
Masaya Yoshikawa, Hidekazu Terai
Route selection algorithm based on integer operation Ant Colony Optimization. IRI (2008)
Masaya Yoshikawa, Hidekazu Terai
The new DFM approach based on a genetic algorithm. Artif. Life Robotics 11 (1) (2007)
Masaya Yoshikawa, Hidekazu Terai
Architecture for high-speed Ant Colony Optimization. IRI (2007)
Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. CICC (2007)
Masaya Yoshikawa, Hidekazu Terai
Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption. J. Adv. Comput. Intell. Intell. Informatics 11 (2) (2007)
Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai
Immune Algorithm Processor. CATA (2006)
Masaya Yoshikawa, Hidekazu Terai
Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. SERA (2006)
Masaya Yoshikawa, Hidekazu Terai
Co-evolutionary robotics using two kinds of neural networks. CAINE (2006)
Masaya Yoshikawa, Hidekazu Terai
Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation. J. Adv. Comput. Intell. Intell. Informatics 10 (1) (2006)
Masaya Yoshikawa, Hidekazu Terai
Hybrid genetic algorithm engine for high-speed floorplanning. ECCTD (2005)
Masaya Yoshikawa, Hidekazu Terai
Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. SERA (2005)
Masaya Yoshikawa, Hidekazu Terai
Performance driven placement technique based on collaboration of software and hardware. Congress on Evolutionary Computation (2005)
Masaya Yoshikawa, Hidekazu Terai
A Hierarchical Parallel Placement Technique based on Genetic Algorithm. ISDA (2005)
Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi
VLSI processor architecture for real-time GA processing and PE-VLSI design. ISCAS (3) (2004)
Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi
Scalable GA processor architecture and its implementation of processor-element. ICASSP (2002)