Shinya Honda

Publication Activity (10 Years)

Years Active: 2003-2021
Publications (10 Years): 14

Top Topics

Driver Assistance

Top Venues

IPSJ Trans. Syst. LSI Des. Methodol.

Inf. Media Technol.

J. Inf. Process.

SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI

Publications

Tomoaki Kawada, Shinya Honda, Yutaka Matsubara, Hiroaki Takada
TZmCFI: RTOS-Aware Control-Flow Integrity Using TrustZone for Armv8-M. Int. J. Parallel Program. 49 (2) (2021)
Toki Matsumoto, Yukikazu Nakamoto, Ryota Yamamoto, Shinya Honda, Kazutoshi Wakabayashi
Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI (2019)
Tomohiro Tsuruya, Musashi Danseko, Katsuhiko Sasaki, Shinya Honda, Ryo Takeda
Process monitoring of deep drawing using machine learning. AIM (2019)
Shu Takemoto, Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa, Shinya Honda, Ryo Kurachi
Performance Evaluation of CAESAR Authenticated Encryption on SROS2. AICCC (2019)
Tasuku Ishigooka, Shinya Honda, Hiroaki Takada
Cost-Effective Redundancy Approach for Fail-Operational Autonomous Driving System. ISORC (2018)
Masataka Ogawa, Shinya Honda, Hiroaki Takada
Efficient Approach to Ensure Temporal Determinism in Automotive Control Systems. ISED (2018)
Akihiro Yamaguchi, Yousuke Watanabe, Kenya Sato, Yukikazu Nakamoto, Yoshiharu Ishikawa, Shinya Honda, Hiroaki Takada
In-vehicle Distributed Time-critical Data Stream Management System for Advanced Driver Assistance. J. Inf. Process. 25 (2017)
Kazuto Shigihara, Shinya Honda, Hiroaki Takada
Test Program Generator for AUTOSAR OS. EDCC (2017)
Kunihiko Kaneko, Shinya Honda
A Map Database System for Route Navigation with Multiple Transit Points and Destination Points. IIAI-AAI (2016)
Shinya Honda, Yoshihiro Narita, Naohiro Kida
Adaptive control for vibration suppression by using self-organization map. ASCC (2015)
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Akihiro Yamaguchi, Yukikazu Nakamoto, Kenya Sato, Yoshiharu Ishikawa, Yousuke Watanabe, Shinya Honda, Hiroaki Takada
AEDSMS: Automotive Embedded Data Stream Management System. ICDE (2015)
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip. Inf. Media Technol. 10 (3) (2015)
Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro
System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler. J. Inf. Process. 23 (5) (2015)
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. IPSJ Trans. Syst. LSI Des. Methodol. 7 (2014)
Yuki Ando, Masataka Ogawa, Yuya Mizoguchi, Kouta Kumagai, Miaw Torng-Der, Shinya Honda
A Case Study of FPGA Blokus Duo Solver by System-Level Design. SIGARCH Comput. Archit. News 42 (4) (2014)
Yukikazu Nakamoto, Akihiro Yamaguchi, Kenya Sato, Shinya Honda, Hiroaki Takada
Toward Data-Centric Software Architecture for Automotive Systems - Embedded Data Stream Processing Approach. UIC/ATC/ScalCom (2014)
Satoshi Katsunuma, Shinya Honda, Kenya Sato, Yousuke Watanabe, Yukikazu Nakamoto, Hiroaki Takada
Real-Time-Aware Embedded DSMS Applicable to Advanced Driver Assistance Systems. SRDS Workshops (2014)
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. Inf. Media Technol. 9 (1) (2014)
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs. FCCM (2014)
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. Inf. Media Technol. 8 (4) (2013)
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration. IESS (2013)
Daniel Sangorrín, Shinya Honda, Hiroaki Takada
Reliable and Efficient Dual-OS Communications for Real-Time Embedded Virtualization. Inf. Media Technol. 8 (1) (2013)
Yukikazu Nakamoto, Masanori Okamoto, Mohanmed Bhuiya, Akihiro Yamaguchi, Kenya Sato, Shinya Honda, Hiroaki Takada
Android Platform Based on Vehicle Embedded Data Stream Processing. UIC/ATC (2013)
Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. Int. J. Reconfigurable Comput. 2013 (2013)
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
Comparison of Preemption Schemes for Partially Reconfigurable FPGAs. IEEE Embed. Syst. Lett. 4 (2) (2012)
Yutaka Matsubara, Yasumasa Sano, Shinya Honda, Hiroaki Takada
An Open-Source Flexible Scheduling Simulator for Real-Time Applications. ISORC (2012)
Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
A Fast Performance Estimation Framework for System-Level Design Space Exploration. IPSJ Trans. Syst. LSI Des. Methodol. 5 (2012)
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis. HPCC-ICESS (2012)
Kentaro Tomii, Yoshito Sawada, Shinya Honda
Convergent evolution in structural elements of proteins investigated using cross profile analysis. BMC Bioinform. 13 (2012)
Daniel Sangorrín, Shinya Honda, Hiroaki Takada
Reliable Device Sharing Mechanisms for Dual-OS Embedded Trusted Computing. TRUST (2012)
Daniel Sangorrín, Shinya Honda, Hiroaki Takada
Integrated Scheduling for a Reliable Dual-OS Monitor. Inf. Media Technol. 7 (2) (2012)
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs. IEICE Trans. Inf. Syst. (2) (2012)
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems. ISOCC (2011)
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. ReConFig (2011)
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
Fast design space exploration for mixed hardware-software embedded systems. ISOCC (2011)
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems. FPL (2010)
Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. DELTA (2010)
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
Automatic communication synthesis with hardware sharing for design space exploration. ISCAS (2010)
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. J. Inf. Process. 17 (2009)
Yoshito Sawada, Shinya Honda
ProSeg: a database of local structures of protein segments. J. Comput. Aided Mol. Des. 23 (3) (2009)
Masakazu Sekijima, Junta Doi, Shinya Honda, Tamotsu Noguchi, Shigenori Shimizu, Yutaka Akiyama
Free Energy Landscape Analysis System Based on Parallel Molecular Dynamics Simulation. Inf. Media Technol. 3 (1) (2008)
Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada
Embedded System Covalidation with RTOS Model and FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 1 (2008)
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
CHStone: A benchmark program suite for practical C-based high-level synthesis. ISCAS (2008)
Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada
Embedded System Covalidation with RTOS Model and FPGA. Inf. Media Technol. 3 (4) (2008)
Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. ASP-DAC (2007)
Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. ICESS (2007)
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Function Call Optimization for Efficient Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2007)
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. ICESS (2007)
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. ACM Great Lakes Symposium on VLSI (2007)
Masaki Yamamoto, Shinya Honda, Hiroaki Takada, Kiyoshi Agusa, Hiroyuki Tomiyama, Kenji Mase, Nobuo Kawaguchi, Nobuyuki Kaneko
Practice and analysis of an extension course for training trainers of embedded software. SIGBED Rev. 4 (1) (2007)
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
Function Call Optimization in Behavioral Synthesis. DSD (2006)
Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
Cosimulation of ITRON-based embedded software with SystemC. HLDVT (2005)
Hiroyuki Tomiyama, Shin-ichiro Chikada, Shinya Honda, Hiroaki Takada
An RTOS-Based Design and Validation Methodology for Embedded Systems. IEICE Trans. Inf. Syst. (9) (2005)
Masaki Yamamoto, Hiroyuki Tomiyama, Hiroaki Takada, Kiyoshi Agusa, Kenji Mase, Nobuo Kawaguchi, Shinya Honda, Nobuyuki Kaneko
NEXCESS: Nagoya university extension courses for embedded software specialists. SIGBED Rev. 2 (4) (2005)
Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada
RTOS-centric hardware/software cosimulator for embedded system design. CODES+ISSS (2004)
Hiroaki Takada, Shinya Honda, Reiji Nishiyama, Hiroshi Yuyama
Hardware/Software Co-Configuration for Multiprocessor SoPC. WSTFES (2003)
Shinya Honda, Hiroaki Takada
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device. DATE (2003)