Kazutoshi Wakabayashi

Publication Activity (10 Years)

Years Active: 1985-2024
Publications (10 Years): 8

Top Topics

Fpga Implementation

Parameter Optimization

Reconfigurable Architecture

High Level Synthesis

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEEE Embed. Syst. Lett.

SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI

Publications

Kento Mishima, Naoya Niwa, Kazutoshi Wakabayashi, Hiroe Iwasaki
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions. COOL CHIPS (2024)
Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool. HEART (2021)
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC (2020)
Toki Matsumoto, Yukikazu Nakamoto, Ryota Yamamoto, Shinya Honda, Kazutoshi Wakabayashi
Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI (2019)
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10 (4) (2018)
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL (2016)
Takashi Kishimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Hiroyuki Ochi
Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC (2015)
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Kazutoshi Wakabayashi, Takashi Takenaka, Hiroaki Inoue
Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU. ASP-DAC (2014)
Kazutoshi Wakabayashi
Reconfigurable chip advantage compared with GPGPU from the compiler perspective. FPT (2013)
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig (2013)
Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
Machine learning predictive modelling high-level synthesis design space exploration. IET Comput. Digit. Tech. 6 (3) (2012)
Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
Divide and conquer high-level synthesis design space exploration. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
Precision tunable RTL macro-modelling cycle-accurate power estimation. IET Comput. Digit. Tech. 5 (2) (2011)
Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. ISLPED (2010)
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano
Wire congestion aware synthesis for a dynamically reconfigurable processor. FPT (2010)
Wolfgang Rosenstiel, Kazutoshi Wakabayashi
CODES+ISSS 2009 guest editors' introduction. Des. Autom. Embed. Syst. 14 (3) (2010)
Kazutoshi Wakabayashi
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Benjamin Carrión Schäfer, Ashish Trambadia, Kazutoshi Wakabayashi
Design of complex image processing systems in ESL. ASP-DAC (2010)
Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
Design Space Exploration Acceleration Through Operation Clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (1) (2010)
Benjamin Carrión Schäfer, Yusuke Iguchi, Wataru Takahashi, Shingo Nagatani, Kazutoshi Wakabayashi
Fixed Point Data Type Modeling for High Level Synthesis. IEICE Trans. Electron. (3) (2010)
Kazutoshi Wakabayashi
Real-time multimedia with C compiler for Hardware. ESTIMedia (2010)
Reinaldo A. Bergamaschi, Luca Benini, Krisztián Flautner, Wido Kruijtzer, Alberto L. Sangiovanni-Vincentelli, Kazutoshi Wakabayashi
The State of ESL Design [Roundtable]. IEEE Des. Test Comput. 25 (6) (2008)
Liangwei Ge, Song Chen, Kazutoshi Wakabayashi, Takashi Takenaka, Takeshi Yoshimura
Max-Flow Scheduling in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2007)
Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi
Synthesizing "Verification Aware" Models: Why and How? VLSI Design (2007)
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing
High-level synthesis challenges and solutions for a dynamically reconfigurable processor. ICCAD (2006)
Kazutoshi Wakabayashi
Unified Representation for Speculative Scheduling: Generalized Condition Vector. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Kazutoshi Wakabayashi
System LSI design with C-based behavioral synthesis and verification. ISCAS (6) (2005)
Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe
Are we ready for system-level synthesis? ASP-DAC (2005)
Kazutoshi Wakabayashi
C-based behavioral synthesis and verification analysis on industrial design examples. ASP-DAC (2004)
Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima
Stream applications on the dynamically reconfigurable processor. FPT (2004)
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM (2004)
Hidefumi Kurokawa, Hiroyuki Ikegami, Motohide Otsubo, Kiyoshi Asao, Kazuhisa Kirigaya, Katsuya Misu, Satoshi Takahashi, Tetsuji Kawatsu, Kouji Nitta, Hiroshi Ryu, Kazutoshi Wakabayashi, Minoru Tomobe, Wataru Takahashi, Akira Mukouyama, Takashi Takenaka
Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2003)
Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi
Property-Specific Testbench Generation for Guided Simulation. VLSI Design (2002)
Kazutoshi Wakabayashi
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2002)
Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar
Property-specific witness graph generation for guided simulation. DATE (2001)
Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. CICC (2000)
Kazutoshi Wakabayashi, Takumi Okamoto
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (12) (2000)
Kazutoshi Wakabayashi
C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber". DATE (1999)
Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi
Controller-based power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (10) (1999)
Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
Power Management Techniques for Control-Flow Intensive Designs. DAC (1997)
Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
Controller re-specification to minimize switching activity in controller/data path circuits. ISLPED (1996)
Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi
Design-for-debugging of application specific designs. ICCAD (1995)
Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita
Multi-Level Logic Minimization Based on Multi-Signal Implications. DAC (1995)
Jan M. Rabaey, Miodrag Potkonjak, Kazutoshi Wakabayashi
Efficient throughput optimization of feedback linear computations using generalized Horner's scheme. ICASSP (1995)
Kazutoshi Wakabayashi, Hirohito Tanaka
Global Scheduling Independent of Control Dependencies Based on Condition Vectors. DAC (1992)
Kazutoshi Wakabayashi, Takeshi Yoshimura
A resource sharing and control synthesis method for conditional branches. ICCAD (1989)
Gotaro Odawara, Kazuhiko Iijima, Kazutoshi Wakabayashi
Knowledge-based placement technique for printed wiring boards. DAC (1985)