Hiroe Iwasaki

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 16

Top Topics

Top Venues

IEICE Trans. Electron.

Publications

Kento Mishima, Naoya Niwa, Kazutoshi Wakabayashi, Hiroe Iwasaki
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions. COOL CHIPS (2024)
Daisuke Kobayashi, Ken Nakamura, Masaki Kitahara, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki
A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming. IEICE Trans. Inf. Syst. 106 (1) (2023)
Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. IEICE Trans. Electron. 106 (6) (2023)
Masayuki Sato, Yuya Omori, Ryusuke Egawa, Ken Nakamura, Daisuke Kobayashi, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. PDCAT (2022)
Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. COOL CHIPS (2022)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS (2022)
Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. IEICE Trans. Electron. (3) (2020)
Takayuki Onishi, Yuya Omori, Ken Nakamura, Hiroe Iwasaki, Atsushi Shimizu
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation. ISCAS (2019)
Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. COOL CHIPS (2019)
Daisuke Kobayashi, Ken Nakamura, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki
A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control. GLOBECOM (2019)
Yuya Omori, Ken Nakamura, Takayuki Onishi, Daisuke Kobayashi, Tatsuya Osawa, Hiroe Iwasaki
4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay. ICECS (2019)
Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Yasuyuki Nakajima, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu
An HEVC real-time encoding system with high quality HDR color representations. ICCE (2018)
Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu
A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K. IEEE Trans. Multi Scale Comput. Syst. 4 (4) (2018)
Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu
A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations. IEEE Trans. Consumer Electron. 64 (4) (2018)
Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu
A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K. COOL Chips (2017)
Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. Hot Chips Symposium (2015)
Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. VLSIC (2015)
Mitsuo Ikeda, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Hiroe Iwasaki, Yasuyuki Nakajima, Koyo Nitta, Yasuko Takahashi, Kazuya Yokohari, Daisuke Kobayashi, Kazuto Kamikura, Hirohisa Jozawa
MVC real-time video encoder for full-HDTV 3D video. ICCE (2012)
Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. IEICE Trans. Electron. (4) (2012)
Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. IEEE Trans. Very Large Scale Integr. Syst. 15 (9) (2007)
Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima
MPEG-2 real-time software CODEC for full-duplex transmission application over IP networks. Systems and Computers in Japan 36 (2) (2005)
Minoru Inamori, Hiroe Iwasaki, Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Yoshiyuki Yashima
New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI. IEEE Trans. Consumer Electron. 51 (2) (2005)
Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. DATE (2003)
Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo
A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems. CICC (2003)
Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Takeshi Ogura
Advanced concurrent design environment for multimedia system LSIs. Systems and Computers in Japan 33 (14) (2002)
Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai
SuperENC: MPEG-2 video encoder chip. IEEE Micro 19 (4) (1999)
Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura
On-Chip Multimedia Real-Time OS and its MPEG-2 Applications. RTCSA (1999)
Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura
High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. DATE (1999)