Masanori Hariyama

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 30

Top Topics

Database Management

Pipelined Architecture

Design Space Exploration

Spatial And Temporal

Top Venues

J. Supercomput.

Publications

Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Performance evaluation of Word2vec accelerators exploiting spatial and temporal parallelism on DDR/HBM-based FPGAs. J. Supercomput. 80 (12) (2024)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU. J. Supercomput. 78 (6) (2022)
Kosiro Obata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++. MWSCAS (2022)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS (2022)
Hasitha Muthumala Waidyasooriya, Shutaro Ishihara, Masanori Hariyama
Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism. PDCAT (2022)
Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators. J. Supercomput. 78 (1) (2022)
Mitsuhiro Okada, Takayuki Suzuki, Naoya Nishio, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services. IEEE Trans. Cloud Comput. 10 (2) (2022)
Hasitha Muthumala Waidyasooriya, Yuta Ohma, Masanori Hariyama
FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model. MCSoC (2022)
Hasitha Muthumala Waidyasooriya, Hiroki Oshiyama, Yuya Kurebayashi, Masanori Hariyama, Masayuki Ohzeki
A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory. IEEE Access 10 (2022)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Shunsuke Tatsumi, Masanori Hariyama, Koichi Ito, Takafumi Aoki
An FPGA accelerator for PatchMatch multi-view stereo using OpenCL. J. Real Time Image Process. 17 (2) (2020)
Chia-Yin Liu, Yi-Jung Chen, Masanori Hariyama
Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. SAC (2020)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism. IEEE Access 8 (2020)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masamichi J. Miyama, Masayuki Ohzeki
OpenCL-based design of an FPGA accelerator for quantum annealing simulation. J. Supercomput. 75 (8) (2019)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability. IEEE Access 7 (2019)
Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, Masanori Hariyama
Benchmarks for FPGA-Targeted High-Level-Synthesis. CANDAR (2019)
Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Taisuke Ono, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa
A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA. CANDAR Workshops (2019)
Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation. CANDAR (2019)
Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa
FPGA-Based Acceleration of Word2vec using OpenCL. ISCAS (2019)
Yuki Hiradate, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaaki Harada
Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems. SCFA (2018)
Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama
Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. ISPACS (2018)
Yaya Watanabe, Masanori Hariyama, Mitsugi Shimoda
A System for Estimating Optimal Resected Liver Regions Considering Practical Surgical Constraints. ISPACS (2018)
Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions. Int. J. Reconfigurable Comput. 2017 (2017)
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunsuke Tatsumi, Masanori Hariyama
OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology. IEEE Trans. Parallel Distributed Syst. 28 (5) (2017)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL. Int. J. Networked Distributed Comput. 5 (1) (2017)
Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tsukasa Ishigaki
Architecture of an FPGA accelerator for LDA-based inference. SNPD (2017)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform. IEEE Trans. Parallel Distributed Syst. 27 (5) (2016)
Shunsuke Tatsumi, Masanori Hariyama, Norikazu Ikoma
Evaluation of an OpenCL-Based FPGA Platform for Particle Filter. J. Adv. Comput. Intell. Intell. Informatics 20 (5) (2016)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL. ICIS (2016)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL. ICIS (2016)
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama
Hardware-oriented succinct-data-structure based on block-size-constrained compression. SoCPaR (2015)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. J. Comput. Eng. 2014 (2014)
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. APCCAS (2014)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. EMBC (2013)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. J. Multiple Valued Log. Soft Comput. 20 (5-6) (2013)
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design. IEICE Trans. Inf. Syst. (8) (2013)
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Trans. Electron. (8) (2012)
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS (2012)
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. ISCAS (2012)
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. (2) (2012)
Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Trans. Electron. (12) (2012)
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Technol. 21 (10) (2011)
Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama
A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? J. Multiple Valued Log. Soft Comput. 17 (5-6) (2011)
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2011)
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC (2011)
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Trans. Electron. (10) (2011)
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA (2010)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Trans. Inf. Syst. (8) (2010)
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Trans. Electron. (8) (2010)
Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA (2010)
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA (2010)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA (2009)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA (2009)
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA (2009)
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. IEEE Trans. Very Large Scale Integr. Syst. 17 (3) (2009)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Trans. Electron. (4) (2009)
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC (2009)
Masanori Hariyama, Keita Tanji, Michitaka Kameyama
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA (2009)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA (2008)
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Trans. Electron. (9) (2008)
Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama
FPGA implementation of a vehicle detection algorithm using three-dimensional information. IPDPS (2008)
Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA (2008)
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
Memory Allocation for Multi-Resolution Image Processing. IEICE Trans. Inf. Syst. (10) (2008)
Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Trans. Electron. (4) (2008)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. IEICE Trans. Electron. (4) (2008)
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. ISVLSI (2006)
Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ISMVL (2006)
Masanori Hariyama, Michitaka Kameyama
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. APCCAS (2006)
Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. IEICE Trans. Electron. (11) (2006)
Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. IPDPS (2006)
W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. APCCAS (2006)
Masanori Hariyama, Sho Ogata, Michitaka Kameyama
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. IEICE Trans. Electron. (11) (2006)
Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. IEEE Trans. Computers 54 (6) (2005)
Masanori Hariyama
Editorial: VLSI Computing for Real-World Intelligent Systems. J. Robotics Mechatronics 17 (4) (2005)
Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. ISVLSI (2005)
Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. IEICE Trans. Inf. Syst. (7) (2005)
Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. IPDPS (2005)
Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ISVLSI (2004)
Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. ISVLSI (2004)
Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. ISVLSI (2002)
Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama
VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. ICRA (2001)
Masanori Hariyama, Michitaka Kameyama
Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture. J. Robotics Mechatronics 12 (5) (2000)
Hideki Kazama, Masanori Hariyama, Michitaka Kameyama
Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction. J. Robotics Mechatronics 12 (5) (2000)
Masanori Hariyama, Michitaka Kameyama
Path Planning Based on Distance Transformation and Its VLSI Implementation. J. Robotics Mechatronics 12 (5) (2000)
Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama
Architecture of a high-performance stereo vision VLSI processor. Adv. Robotics 14 (5) (2000)
Masanori Hariyama, Michitaka Kameyama
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. ICRA (1998)
Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. Systems and Computers in Japan 28 (2) (1997)
Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama
Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects. J. Robotics Mechatronics 8 (6) (1996)
Masanori Hariyama, Michitaka Kameyama
Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles. J. Robotics Mechatronics 6 (2) (1994)