Shota Ishihara

Publication Activity (10 Years)

Years Active: 2008-2018
Publications (10 Years): 1

Top Topics

Delay Insensitive

Top Venues

J. Multiple Valued Log. Soft Comput.

IEICE Trans. Electron.

Publications

Shota Ishihara, Masafumi Hashimoto, Naoki Wakamiya, Masayuki Murata, Yasutaka Kawamoto
A group-based scheduling method for landslide detection system with dense wireless sensor network. ICT-DM (2018)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. J. Multiple Valued Log. Soft Comput. 20 (5-6) (2013)
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Trans. Electron. (8) (2012)
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS (2012)
Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama
A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? J. Multiple Valued Log. Soft Comput. 17 (5-6) (2011)
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC (2011)
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Trans. Electron. (10) (2011)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Trans. Inf. Syst. (8) (2010)
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Trans. Electron. (8) (2010)
Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA (2010)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA (2009)
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA (2009)
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC (2009)
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Trans. Electron. (9) (2008)
Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA (2008)