Michitaka Kameyama

ORCID

Publication Activity (10 Years)

Years Active: 1977-2024
Publications (10 Years): 18

Top Venues

CoRR

ISMVL

IEICE Trans. Inf. Syst.

SMC

Publications

Martin Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze, Abilmansur Rakhmettulayev, Michitaka Kameyama
Geometric Refactoring of Quantum and Reversible Circuits Using Graph Algorithms. IEICE Trans. Inf. Syst. 107 (8) (2024)
Martin Lukac, Michitaka Kameyama
Verification Based Algorithm Selection. IDT (2023)
Martin Lukac, Krzysztof Podlaski, Michitaka Kameyama
Approximate Function Classification. ICCS (1) (2022)
Martin Lukac, Pawel Kerntopf, Michitaka Kameyama
Optimization of LNN Reversible Circuits Using an Analytic Sifting Method. J. Circuits Syst. Comput. 30 (9) (2021)
Martin Lukac, Ayazkhan Bayanov, Albina Li, Kamila Abdiyeva, Nadira Izbassarova, Magzhan Gabidolla, Michitaka Kameyama
Selecting Algorithms Without Meta-features. ICPR Workshops (4) (2020)
Kenichi Takada, Michitaka Kameyama
High-Accuracy Scene Recognition and Its Application to Highly-Safe Intelligent Systems. SMC (2018)
Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
CNOT-Measure Quantum Neural Networks. ISMVL (2018)
Martin Lukac, Michitaka Kameyama, Yevgeniya Migranova
Live-feeling communication: Multi-algorithm approach to the estimation of human intentions. SMC (2017)
Katsuhiko Shimabukuro, Michitaka Kameyama
Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic. ISMVL (2017)
Martin Lukac, Aigerim Bazarbayeva, Michitaka Kameyama
Context Based Visual Content Verification. CoRR (2017)
Martin Lukac, Gerhard W. Dueck, Michitaka Kameyama, Anirban Pathak
Building a Completely Reversible Computer. CoRR (2017)
Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
On Minimal Accuracy Algorithm Selection in Computer Vision and Intelligent Systems. CoRR (2016)
Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
Reasoning and Algorithm Selection Augmented Symbolic Segmentation. CoRR (2016)
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
Symbolic Segmentation Using Algorithm Selection. CoRR (2015)
Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Michitaka Kameyama
Novel VLSI Architectures for Real-World Intelligent Systems. ISMVL (2015)
Martin Lukac, Michitaka Kameyama
An algorithm selection based platform for image understanding using high-level symbolic feedback and machine learning. Int. J. Mach. Learn. Cybern. 6 (3) (2015)
Xu Bai, Michitaka Kameyama
Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI. IEICE Trans. Electron. (10) (2014)
Xu Bai, Michitaka Kameyama
Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network. IEICE Trans. Inf. Syst. (9) (2014)
Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. ISMVL (2014)
Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller
Reversible, Information-Preserving Logic and Its Application. J. Multiple Valued Log. Soft Comput. 23 (3-4) (2014)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. J. Comput. Eng. 2014 (2014)
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. APCCAS (2014)
Martin Lukac, Dipal Shah, Marek A. Perkowski, Michitaka Kameyama
Synthesis of Quantum Arrays from Kronecker Functional Lattice Diagrams. IEICE Trans. Inf. Syst. (9) (2014)
Martin Lukac, Maher Hawash, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf
Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns. DSD (2014)
Martin Lukac, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf, Claudio Moraga
Analysis of Faults in Reversible Computing. ISMVL (2014)
Xu Bai, Michitaka Kameyama
A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme. IEICE Trans. Inf. Syst. (7) (2013)
Maher Hawash, Martin Lukac, Michitaka Kameyama, Marek A. Perkowski
Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format. ISMVL (2013)
Xu Bai, Michitaka Kameyama
Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI. ISMVL (2013)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. EMBC (2013)
Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama
RFID-based localization with Non-Blocking tag scanning. Ad Hoc Networks 11 (8) (2013)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. J. Multiple Valued Log. Soft Comput. 20 (5-6) (2013)
Martin Lukac, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf
Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences. ISMVL (2013)
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design. IEICE Trans. Inf. Syst. (8) (2013)
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Martin Lukac, Michitaka Kameyama
Bayesian Network for algorithm selection: Real-world hierarchy for nodes reduction. iCAST/UMEDIA (2013)
Martin Lukac, Michitaka Kameyama, Kosuke Hiura
Natural image understanding using algorithm selection and high-level feedback. Intelligent Robots and Computer Vision: Algorithms and Techniques (2013)
Xu Bai, Michitaka Kameyama
A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits. IEICE Trans. Electron. (8) (2013)
Martin Lukac, Michitaka Kameyama, Marek A. Perkowski
Quantum Finite State Machines - a Circuit Based Approach. Int. J. Unconv. Comput. 9 (3-4) (2013)
Xu Bai, Michitaka Kameyama
An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net. ISMVL (2013)
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Trans. Electron. (8) (2012)
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS (2012)
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. ISCAS (2012)
Shogo Kisara, Michitaka Kameyama
Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits. ISMVL (2012)
Yoshichika Fujioka, Michitaka Kameyama
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. ISOCC (2012)
Bo Sun, Michitaka Kameyama
Driver's Intention Estimation Based on Bayesian Networks for a Highly-Safe Intelligent Vehicle. J. Robotics Mechatronics 24 (1) (2012)
Xu Bai, Nobuaki Okada, Michitaka Kameyama
A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme. J. Multiple Valued Log. Soft Comput. 20 (1-2) (2012)
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. (2) (2012)
Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski
High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation? J. Multiple Valued Log. Soft Comput. 20 (1-2) (2012)
Xu Bai, Michitaka Kameyama
Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture. ISMVL (2012)
Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Trans. Electron. (12) (2012)
Kan Watanabe, Masaru Fukushi, Michitaka Kameyama
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing. J. Inf. Process. 19 (2011)
Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama
High Performance Tag Singulation for Memory-Less RFID Systems. ICC (2011)
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Technol. 21 (10) (2011)
Maarti nLukac, Marek A. Perkowski, Michitaka Kameyama
Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics CoRR (2011)
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller
Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation. ISMVL (2011)
Kan Watanabe, Masaru Fukushi, Michitaka Kameyama
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing. Inf. Media Technol. 6 (2) (2011)
Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama
Non-blocking tag scanning for passive RFID localization. ISDA (2011)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2011)
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC (2011)
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Trans. Electron. (10) (2011)
Martin Lukac, Marek A. Perkowski, Michitaka Kameyama
Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions. IEEE Congress on Evolutionary Computation (2010)
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA (2010)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Trans. Inf. Syst. (8) (2010)
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Trans. Electron. (8) (2010)
Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama
Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals. ISMVL (2010)
Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA (2010)
Michitaka Kameyama
Foreword. IEICE Trans. Inf. Syst. (8) (2010)
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Nobuaki Okada, Michitaka Kameyama
Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits. IEICE Trans. Inf. Syst. (8) (2010)
Martin Lukac, Michitaka Kameyama, Marek A. Perkowski
Adaptive Selection of Intelligent Processing Modules and its Applications. IC-AI (2010)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA (2010)
Dalia Nashat, Xiaohong Jiang, Michitaka Kameyama
Group Testing Based Detection of Web Service DDoS Attackers. IEICE Trans. Commun. (5) (2010)
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA (2009)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA (2009)
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA (2009)
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. IEEE Trans. Very Large Scale Integr. Syst. 17 (3) (2009)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Trans. Electron. (4) (2009)
Nobuaki Okada, Michitaka Kameyama
Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. ISMVL (2009)
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC (2009)
Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama
Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. ISMVL (2009)
Masanori Hariyama, Keita Tanji, Michitaka Kameyama
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA (2009)
Nobuaki Okada, Michitaka Kameyama
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. ISMVL (2008)
Nobuaki Okada, Michitaka Kameyama
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation. IEICE Trans. Electron. (9) (2008)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA (2008)
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Trans. Electron. (9) (2008)
Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama
FPGA implementation of a vehicle detection algorithm using three-dimensional information. IPDPS (2008)
Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA (2008)
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
Memory Allocation for Multi-Resolution Image Processing. IEICE Trans. Inf. Syst. (10) (2008)
Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Trans. Electron. (4) (2008)
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. IEICE Trans. Electron. (4) (2008)
Tasuku Ito, Michitaka Kameyama
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. ISMVL (2007)
Nobuaki Okada, Michitaka Kameyama
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. J. Multiple Valued Log. Soft Comput. 13 (4-6) (2007)
Tasuku Ito, Michitaka Kameyama
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. J. Multiple Valued Log. Soft Comput. 13 (4-6) (2007)
Nobuaki Okada, Michitaka Kameyama
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. ISMVL (2007)
Michitaka Kameyama
Special Section on VLSI Technology toward Frontiers of New Market. IEICE Trans. Electron. (10) (2007)
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. ISVLSI (2006)

Michitaka Kameyama.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Michitaka Kameyama