Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit.

Zhengfan Xia Shota Ishihara Masanori Hariyama Michitaka Kameyama

Published in: ISCAS (2012)

Keyphrases

high speed
shift register
chip design
digital circuits
logic circuits
asynchronous circuits
computer aided
delay insensitive
logic synthesis
hybrid learning
circuit design
electronic circuits
real time
design methodology
embedded systems
software architecture
design process
user interface