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Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme.
Yoshichika Fujioka
Michitaka Kameyama
Published in:
ISOCC (2012)
Keyphrases
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data transfer
memory size
reduction method
data access
data transmission
data flow
random access
main memory
high speed
file system
databases
external memory
parallel computers
database
low cost
database systems
metadata