Gerhard W. Dueck

Publication Activity (10 Years)

Years Active: 1990-2023
Publications (10 Years): 39

Top Topics

Logic Synthesis

Java Virtual Machine

Memory Management

Nearest Neighbor

Top Venues

Publications

Siri Sahithi Ponangi, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier, Kazuhiro Konno
Java Runtime Optimization for Copying Arrays on AArch64. MECO (2023)
Aaron Graham, Jean-Philippe Legault, Hillary Soontiens, Julie Brown, Stephen A. MacKay, Gerhard W. Dueck, Kenneth B. Kent, Kazuhiro Konno, Daryl Maier
Evaluating the Performance of the Eclipse OpenJ9 JVM JIT Compiler on AArch64. CCECE (2022)
Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler
Template-based mapping of reversible circuits to IBM quantum computers. Microprocess. Microsystems 90 (2022)
Georgiy Krylov, Petar Jelenkovic, Mark Thom, Gerhard W. Dueck, Kenneth B. Kent, Younes Manton, Daryl Maier
Ahead-of-time compilation in eclipse OMR on example of WebAssembly. CASCON (2021)
Arighna Deb, Gerhard W. Dueck, Robert Wille
Exploring the Potential Benefits of Alternative Quantum Computing Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (9) (2021)
Alexandre A. A. de Almeida, Gerhard W. Dueck
Adaptive Integer Linear Programming Model for Optimal Qubit Permutation. IEEE Des. Test 38 (4) (2021)
D. Michael Miller, Gerhard W. Dueck
Function translations and search-based transformation for MVL reversible circuit synthesis. Sci. Comput. Program. 212 (2021)
Damian Diago D'monte, Georgiy Krylov, Younes Manton, Gerhard W. Dueck, Kenneth B. Kent
A lightweight code storage container for the eclipse OMR ahead-of-time compiler. CASCON (2021)
D. Michael Miller, Gerhard W. Dueck
Descending Order Transformation-based Synthesis of MVL Reversible Circuits. ISMVL (2021)
Arighna Deb, Gerhard W. Dueck, Robert Wille
Towards Exploring the Potential of Alternative Quantum Computing Architectures. DATE (2020)
Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler
Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers. DSD (2020)
Damian Diago D'monte, Georgiy Krylov, Daryl Maier, Gerhard W. Dueck, Kenneth B. Kent
An ELF-based storage option for the eclipse OMR ahead-of-time compiler. CASCON (2020)
D. Michael Miller, Gerhard W. Dueck
Search-Based Transformation Synthesis for 3-Valued Reversible Circuits. RC (2020)
Georgiy Krylov, Maria Patrou, Gerhard W. Dueck, Joran Siu
The Evolution of Garbage Collection in V8: Google's JavaScript Engine. MECO (2020)
Abhijit Taware, Kenneth B. Kent, Gerhard W. Dueck, Charlie Gracie
Cold Object Identification and Segregation using Page Protection and Profiling. MECO (2020)
Alexandre Araujo Amaral de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures. ISMVL (2019)
Georgiy Krylov, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier, Irwin D'Souza
Ahead-of-time compilation in OMR: overview and first steps. CASCON (2019)
Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre César Rodrigues da Silva
Efficient Realization of Toffoli and NCV Circuits for IBM QX Architectures. RC (2019)
Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
CNOT Gate Optimizations via Qubit Permutations for IBM's Quantum Architectures. J. Low Power Electron. 15 (2) (2019)
Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
Finding optimal qubit permutations for IBM's quantum computer architectures. SBCCI (2019)
Evandro C. Ferraz, Jeferson de Lima Muniz, Alexandre C. R. da Silva, Gerhard W. Dueck
Synthesis of Majority Expressions through Primitive Function Manipulation. CoRR (2018)
Maria Patrou, Kenneth B. Kent, Gerhard W. Dueck, Charlie Gracie, Aleksandar Micic
NUMA Awareness: Improving Thread and Memory Management. SEAA (2018)
Mark Thom, Gerhard W. Dueck, Kenneth B. Kent, Daryl Maier
A survey of ahead-of-time technologies in dynamic language environments. CASCON (2018)
Gerhard W. Dueck, Anirban Pathak, Md. Mazder Rahman, Abhishek Shukla, Anindita Banerjee
Optimization of Circuits for IBM's five-qubit Quantum Computers. CoRR (2018)
Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
Efficient Realizations of CNOT gates in IBM's Quantum Computers. ISED (2018)
Gerhard W. Dueck, Anirban Pathak, Md. Mazder Rahman, Abhishek Shukla, Anindita Banerjee
Optimization of Circuits for IBM's Five-Qubit Quantum Computers. DSD (2018)
Alexandre A. A. de Almeida, Gerhard W. Dueck, Alexandre C. R. da Silva
Reversible Circuit Optimization Based on Tabu Search. ISMVL (2018)
Maria Patrou, Md. Mahbub Alam, Puya Memarzia, Suprio Ray, Virendra C. Bhavsar, Kenneth B. Kent, Gerhard W. Dueck
DISTIL: a distributed in-memory data processing system for location-based services. SIGSPATIAL/GIS (2018)
Scott Young, Michael Flawn, Gerhard W. Dueck, Kenneth B. Kent, Charlie Gracie
Persistent memory storage of cold regions in the OpenJ9 Java virtual machine. CASCON (2018)
Martin Lukac, Gerhard W. Dueck, Michitaka Kameyama, Anirban Pathak
Building a Completely Reversible Computer. CoRR (2017)
Kim T. Briggs, Baoguo Zhou, Gerhard W. Dueck
Cold object identification in the Java virtual machine. Softw. Pract. Exp. 47 (1) (2017)
Marcel Dombrowski, Konstantin Nasartschuk, Kenneth B. Kent, Gerhard W. Dueck, Charlie Gracie
Thread-group based local heap garbage collection in a simulated runtime environment. CCECE (2016)
Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Ancilla-free synthesis of large reversible functions using binary decision diagrams. J. Symb. Comput. 73 (2016)
Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller
An extension of transformation-based reversible and quantum circuit synthesis. ISCAS (2016)
Md. Mazder Rahman, Konstantin Nasartschuk, Kenneth B. Kent, Gerhard W. Dueck
Trace Files for Automatic Memory Management Systems. VST@SANER (2016)
Nils Przigoda, Gerhard W. Dueck, Robert Wille, Rolf Drechsler
Fault Detection in Parity Preserving Reversible Circuits. ISMVL (2016)
Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits. ISMVL (2016)
Mathias Soeken, Gerhard W. Dueck, D. Michael Miller
A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. RC (2016)
Konstantin Nasartschuk, Marcel Dombrowski, Tristan Basa, Md. Mazder Rahman, Kenneth B. Kent, Gerhard W. Dueck
GarCoSim: A Framework for Automated Memory Management Research and Evaluation. EAI Endorsed Trans. Scalable Inf. Syst. 3 (9) (2016)
Shijie Xu, Qi Guo, Gerhard W. Dueck, David Bremner, Yang Wang
Metis: a smart memory allocator using historical reclamation information. ICOOOLPS@ECOOP (2015)
Md. Mazder Rahman, Mathias Soeken, Gerhard W. Dueck
Dynamic Template Matching with Mixed-Polarity Toffoli Gates. ISMVL (2015)
Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
Self-Inverse Functions and Palindromic Circuits. CoRR (2015)
Md. Mazder Rahman, Gerhard W. Dueck
Synthesis of Linear Nearest Neighbor Quantum Circuits. CoRR (2015)
Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler
Reversible circuit rewriting with simulated annealing. VLSI-SoC (2015)
Kim T. Briggs, Baoguo Zhou, Gerhard W. Dueck
Cold Object Identification in the Java Virtual Machine. CoRR (2015)
Marcel Dombrowski, Konstantin Nasartschuk, Kenneth B. Kent, Gerhard W. Dueck
A survey on object cache locality in automated memory management systems. CCECE (2015)
Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Ancilla-free synthesis of large reversible functions using binary decision diagrams. CoRR (2014)
Md. Mazder Rahman, Gerhard W. Dueck, Joseph D. Horton
An Algorithm for Quantum Template Matching. ACM J. Emerg. Technol. Comput. Syst. 11 (3) (2014)
Anindita Banerjee, Anirban Pathak, Gerhard W. Dueck
Minimal Designs of Reversible Sequential Elements. RC (2014)
Gerhard W. Dueck
Challenges and advances in Toffoli network optimisation. IET Comput. Digit. Tech. 8 (4) (2014)
Md. Mazder Rahman, Gerhard W. Dueck
Optimal Quantum Circuits of Three Qubits. ISMVL (2012)
Majid Mohammadi, Aliakbar Niknafs, Mohammad Eshghi, Gerhard W. Dueck
Design and Optimization of Single and Multiple-Loop Reversible and Quantum Feedback Circuits. J. Circuits Syst. Comput. 21 (3) (2012)
Md. Mazder Rahman, Gerhard W. Dueck
An algorithm to find quantum templates. IEEE Congress on Evolutionary Computation (2012)
Hadi Hosseini, Gerhard W. Dueck
Toffoli Gate Implementation Using The Billiard Ball Model. J. Multiple Valued Log. Soft Comput. 19 (1-3) (2012)
Md. Mazder Rahman, Gerhard W. Dueck
Properties of Quantum Templates. RC (2012)
Gerhard W. Dueck
Synthesis of Toffoli Networks: Status and Challenges. ISED (2012)
Md. Mazder Rahman, Gerhard W. Dueck, Anindita Banerjee
Optimization of Reversible Circuits Using Reconfigured Templates. RC (2011)
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Debugging reversible circuits. Integr. 44 (1) (2011)
Md. Mazder Rahman, Anindita Banerjee, Gerhard W. Dueck, Anirban Pathak
Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit. ISMVL (2011)
Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Window optimization of reversible and quantum circuits. DDECS (2010)
Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Synthesizing multiplier in reversible logic. DDECS (2010)
Hadi Hosseini, Gerhard W. Dueck
Toffoli Gate Implementation Using the Billiard Ball Model. ISMVL (2010)
Yasaman Sanaee, Gerhard W. Dueck
ESOP-Based Toffoli Network Generation with Transformations. ISMVL (2010)
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Exact Synthesis of Elementary Quantum Gate Circuits. J. Multiple Valued Log. Soft Comput. 15 (4) (2009)
Gerhard W. Dueck
Editorial. J. Multiple Valued Log. Soft Comput. 15 (4) (2009)
Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Reversible Logic Synthesis with Output Permutation. VLSI Design (2009)
Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Debugging of Toffoli networks. DATE (2009)
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (5) (2009)
D. Michael Miller, Robert Wille, Gerhard W. Dueck
Synthesizing Reversible Circuits for Irreversible Functions. DSD (2009)
Robert Wille, Hoang Minh Le, Gerhard W. Dueck, Daniel Große
Quantified Synthesis of Reversible Logic. DATE (2008)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne
Quantum Circuit Simplification and Level Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL (2008)
Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL (2008)
Nathan O. Scott, Gerhard W. Dueck
Pairwise decomposition of toffoli gates in a quantum circuit. ACM Great Lakes Symposium on VLSI (2008)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12 (4) (2007)
Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI (2007)
Dmitri Maslov, Gerhard W. Dueck
Level Compaction in Quantum Circuits. IEEE Congress on Evolutionary Computation (2006)
D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
Synthesis of Quantum Multiple-Valued Circuits. J. Multiple Valued Log. Soft Comput. 12 (5-6) (2006)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. Very Large Scale Integr. Syst. 13 (6) (2005)
Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck
Quantum Circuit Simplification Using Templates. DATE (2005)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Toffoli network synthesis with templates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (6) (2005)
D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov
A Synthesis Method for MVL Reversible Logi. ISMVL (2004)
Dmitri Maslov, Gerhard W. Dueck
Reversible cascades with minimal garbage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (11) (2004)
D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
A transformation based algorithm for reversible logic synthesis. DAC (2003)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD (2003)
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
Simplification of Toffoli Networks via Templates. SBCCI (2003)
D. Michael Miller, Gerhard W. Dueck
On the Size of Multiple-Valued Decision Diagrams. ISMVL (2003)
Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko
On the number of generators for transeunt triangles. Discret. Appl. Math. 108 (3) (2001)
Ping Wang, Gerhard W. Dueck, S. MacMillan
Using simulated annealing to construct extremal graphs. Discret. Math. 235 (1-3) (2001)
Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL (2000)
Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (11) (2000)
Gerhard W. Dueck, Mou Hu, Blair Fraser
A Super Switch Algebra for Quantum Device Based Systems. ISMVL (1999)
Blair Fraser, Gerhard W. Dueck
Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. ISMVL (1998)
Gerhard W. Dueck, Jon T. Butler
Multiple-Valued Logic Operations with Universal Literals. ISMVL (1994)
Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL (1992)
Gerhard W. Dueck
Direct Cover MVL Minimization with Cost-Tables. ISMVL (1992)
Gerhard W. Dueck, G. H. John van Rees
On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. ISMVL (1991)
Gerhard W. Dueck, D. Michael Miller
RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL (1990)