Parthasarathy P. Tirumalai

Publication Activity (10 Years)

Years Active: 1990-1992
Publications (10 Years): 0

Publications

B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai
Code generation schema for modulo scheduled loops. MICRO (1992)
B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker
Register Allocation for Software Pipelined Loops. PLDI (1992)
Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL (1992)
Parthasarathy P. Tirumalai, Jon T. Butler
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. IEEE Trans. Computers 40 (2) (1991)
Parthasarathy P. Tirumalai, Varadarajan G. Vadakkencherry
Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays. ISMVL (1991)
Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker
Parallelization of WHILE loops on pipelined architectures. J. Supercomput. 5 (2-3) (1991)
Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker
Parallelization of loops with exits on pipelined architectures. SC (1990)