Jon T. Butler

Publication Activity (10 Years)

Years Active: 1973-2024
Publications (10 Years): 25

Top Venues

ISMVL

IEICE Trans. Inf. Syst.

J. Multiple Valued Log. Soft Comput.

FLAP

Publications

Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams. IEICE Trans. Inf. Syst. 107 (8) (2024)
Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama
On the distribution of sensitivities of symmetric Boolean functions. CoRR (2023)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
On Representation of Maximally Asymmetric Functions Based on Decision Diagrams. FLAP 10 (6) (2023)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Decomposition-Based Representation of Symmetric Multiple-Valued Functions. ISMVL (2023)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions. J. Multiple Valued Log. Soft Comput. 38 (3-4) (2022)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
On Decision Diagrams for Maximally Asymmetric Functions. ISMVL (2022)
Jon T. Butler, Tsutomu Sasao
On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions. ISMVL (2022)
Tsutomu Sasao, Jon T. Butler
Linear Decompositions for Multi-Valued Input Classification Functions. ISMVL (2021)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions. ISMVL (2021)
Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama
Properties of Multiple-Valued Partition Functions. ISMVL (2020)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
On Optimum Linear Decomposition of Symmetric Index Generation Functions. ISMVL (2020)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions. ISMVL (2019)
Jon T. Butler, Tsutomu Sasao
Realizing all Index Generation Functions by the Row-Shift Method. ISMVL (2019)
Jon T. Butler, Tsutomu Sasao
Maximally Asymmetric Multiple-Valued Functions. ISMVL (2019)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions. FLAP 5 (9) (2018)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions. ISMVL (2018)
Jon T. Butler, Tsutomu Sasao
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions. ISMVL (2018)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions. ISMVL (2017)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions. IEICE Trans. Inf. Syst. (8) (2017)
Vincent C. Gaudet, Jon T. Butler, Robert Wille, Naofumi Homma
Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (1) (2016)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
An Efficient Heuristic for Linear Decomposition of Index Generation Functions. ISMVL (2016)
Carole J. Etherington, Matthew W. Anderson, Eric Bach, Jon T. Butler, Pantelimon Stanica
A Parallel Approach in Computing Correlation Immunity up to Six Variables. Int. J. Found. Comput. Sci. 27 (4) (2016)
Jon T. Butler, Tsutomu Sasao
A set partition number system. Australas. J Comb. 65 (2016)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems. ISMVL (2015)
Jon T. Butler, Tsutomu Sasao
High-Speed Hardware Partition Generation. ACM Trans. Reconfigurable Technol. Syst. 7 (4) (2015)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators. J. Multiple Valued Log. Soft Comput. 23 (3-4) (2014)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams. ISMVL (2014)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems. IEICE Trans. Inf. Syst. (9) (2014)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components. J. Multiple Valued Log. Soft Comput. 22 (1-2) (2014)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems. ISMVL (2013)
Jon T. Butler, Tsutomu Sasao
Hardware Index to Set Partition Converter. ARC (2013)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Analysis of Multi-state Systems with Multi-state Components Using EVMDDs. ISMVL (2012)
Jon T. Butler, Tsutomu Sasao
Hardware Index to Permutation Converter. IPDPS Workshops (2012)
Jon T. Butler, Tsutomu Sasao
Index to Constant Weight Codeword Converter. ARC (2011)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Numeric Function Generators Using Piecewise Arithmetic Expressions. ISMVL (2011)
Jon T. Butler, Tsutomu Sasao
Fast Hardware Computation of x Mod z. IPDPS Workshops (2011)
Jon T. Butler, C. L. Frenzen, Njuguna Macaria, Tsutomu Sasao
A fast segmentation algorithm for piecewise polynomial numeric function generators. J. Comput. Appl. Math. 235 (14) (2011)
C. L. Frenzen, Tsutomu Sasao, Jon T. Butler
On the number of segments needed in a piecewise linear approximation. J. Comput. Appl. Math. 234 (2) (2010)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. ISMVL (2010)
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Trans. Inf. Syst. (8) (2010)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams. IEICE Trans. Inf. Syst. (8) (2010)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
J. L. Shafer, S. W. Schneider, Jon T. Butler, Pantelimon Stanica
Enumeration of Bent Boolean Functions by Reconfigurable Computer. FCCM (2010)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. ISMVL (2009)
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL (2009)
Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao
Programmable Numerical Function Generators for Two-Variable Functions. DSD (2008)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Numerical function generators using bilinear interpolation. FPL (2008)
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
Numerical Function Generators Using LUT Cascades. IEEE Trans. Computers 56 (6) (2007)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. ASP-DAC (2007)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. DSD (2007)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Tsutomu Sasao, Jon T. Butler
Implementation of Multiple-Valued CAM Functions by LUT Cascades. ISMVL (2006)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. ASP-DAC (2006)
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Hui Qin, Tsutomu Sasao, Jon T. Butler
Implementation of LPM Address Generators on FPGAs. ARC (2006)
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
Programmable Numerical Function Generators: Architectures and Synthesis Method. FPL (2005)
Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams. J. Multiple Valued Log. Soft Comput. 11 (5-6) (2005)
Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura
Average Path Length of Binary Decision Diagrams. IEEE Trans. Computers 54 (9) (2005)
Tsutomu Sasao, Jon T. Butler
A fast method to derive minimum SOPs for decomposable functions. ASP-DAC (2004)
Jon T. Butler, Tsutomu Sasao
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions. ISMVL (2003)
Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi
Bi-Partition of Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Tsutomu Sasao, Jon T. Butler
Worst and Best Irredundant Sum-of-Products Expressions. IEEE Trans. Computers 50 (9) (2001)
Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko
On the number of generators for transeunt triangles. Discret. Appl. Math. 108 (3) (2001)
Tsutomu Sasao, Jon T. Butler
On the minimization of SOPs for bi-decomposition functions. ASP-DAC (2001)
Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL (2000)
Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (11) (2000)
Jon T. Butler, Tsutomu Sasao
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. ISMVL (1998)
Kriss A. Schueller, Jon T. Butler
Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. IEEE Trans. Computers 46 (2) (1997)
Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. IEEE Trans. Computers 46 (4) (1997)
Tsutomu Sasao, Jon T. Butler
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. ISMVL (1997)
Tsutomu Sasao, Jon T. Butler
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. ISMVL (1996)
Jon T. Butler, J. L. Nowlin, Tsutomu Sasao
Planarity in ROMDD's of Multiple-Valued Symmetric Functions. ISMVL (1996)
Tsutomu Sasao, Jon T. Butler
Planar Multiple-Valued Decision Diagrams. ISMVL (1995)
Tsutomu Sasao, Jon T. Butler
A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. ISMVL (1994)
Gerhard W. Dueck, Jon T. Butler
Multiple-Valued Logic Operations with Universal Literals. ISMVL (1994)
Jon T. Butler, Tsutomu Sasao
Multiple-Valued Combinational Circuits with Feedback. ISMVL (1994)
Cem Yildirim, Jon T. Butler, Chyan Yang
Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing. ISMVL (1993)
Susan W. Butler, Jon T. Butler
Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991. ISMVL (1992)
Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL (1992)
Kriss A. Schueller, Jon T. Butler
On the Design of Cost-Tables for Realizing Multiple-Valued Circuits. IEEE Trans. Computers 41 (2) (1992)
Parthasarathy P. Tirumalai, Jon T. Butler
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. IEEE Trans. Computers 40 (2) (1991)
Young-hoon Chang, Jon T. Butler
The Design of Current Mode CMOS Multiple-Valued Circuits. ISMVL (1991)
Jon T. Butler, Kriss A. Schueller
Worst Case Number of Terms in Symmetric Multiple-Valued Functions. ISMVL (1991)
Jon T. Butler, Kriss A. Schueller
On the Equivalence of Cost Functions in the Design of Circuits by Costtable. IEEE Trans. Computers 39 (6) (1990)
Joo-Kang Lee, Jon T. Butler
A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs. IEEE Trans. Computers 39 (10) (1990)
John M. Yurchak, Jon T. Butler
HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays. ISMVL (1990)
Jon T. Butler, Hans G. Kerkhoff, Siep Onneweer
A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach. ISMVL (1990)
Edward A. Bender, Jon T. Butler
On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions. IEEE Trans. Computers 38 (1) (1989)
Jon T. Butler
Multiple-Valued Logic - Guest Editor's Introduction. Computer 21 (4) (1988)
Jon T. Butler, Hans G. Kerkhoff
Multiple-Valued CCD Circuits. Computer 21 (4) (1988)
Edward A. Bender, Jon T. Butler
Enumeration of Structured Flowcharts J. ACM 32 (3) (1985)
Jon T. Butler
On the relationship between propagating context-dependent lindenmayer systems and cellular automata systems. Inf. Sci. 28 (1) (1982)
Jon T. Butler
Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms. IEEE Trans. Computers 30 (8) (1981)
Patrick E. White, Jon T. Butler
Synthesis of One-Dimensional Binary Scope-2 Flexible Cellular Systems from Initial Final Configuration Pairs Inf. Control. 46 (3) (1980)
Jon T. Butler
Synthesis of One-Dimensional Binary Cellular Automata Systems from Composite Local Maps Inf. Control. 43 (3) (1979)
Jon T. Butler
Decomposable Maps in General Tessellation Structures. J. Comput. Syst. Sci. 18 (1) (1979)
Jon T. Butler
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates. J. ACM 25 (3) (1978)
Edward A. Bender, Jon T. Butler
Asymptotic Aproximations for the Number of Fanout-Free Functions. IEEE Trans. Computers 27 (12) (1978)
Jon T. Butler
Tandem Networks of Universal Cells. IEEE Trans. Computers 27 (9) (1978)
Jon T. Butler
Restricted Cellular Networks. IEEE Trans. Computers 25 (11) (1976)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jon T. Butler