Munehiro Matsuura

Publication Activity (10 Years)

Years Active: 1997-2016
Publications (10 Years): 2

Top Topics

Scanning Devices

Deterministic Finite Automata

Multi Valued Decision Diagrams

Top Venues

IEICE Trans. Inf. Syst.

J. Multiple Valued Log. Soft Comput.

Publications

Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto
). J. Multiple Valued Log. Soft Comput. 26 (1-2) (2016)
Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (1) (2016)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. IEICE Trans. Inf. Syst. (2) (2015)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K). ISMVL (2014)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
) Machines. IEICE Trans. Inf. Syst. (9) (2014)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs. J. Multiple Valued Log. Soft Comput. 23 (3-4) (2014)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition. IEICE Trans. Inf. Syst. (8) (2013)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
An Architecture for IPv6 Lookup Using Parallel Index Generation Units. ARC (2013)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A packet classifier using LUT cascades based on EVMDDS (k). FPL (2013)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. ISMVL (2013)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. Microprocess. Microsystems 36 (8) (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. ARC (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. IEICE Trans. Inf. Syst. (2) (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. ISMVL (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. J. Multiple Valued Log. Soft Comput. 19 (1-3) (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. ISMVL (2011)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Regular Expression Matching Circuit Based on a Decomposed Automaton. ARC (2011)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Comparison of Architectures for Various Decision Diagram Machines. ISMVL (2010)
Hiroshi Nakahara, Tsutomu Sasao, Munehiro Matsuura
A regular expression matching using non-deterministic finite automaton. MEMOCODE (2010)
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Trans. Inf. Syst. (8) (2010)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Packet Classifier Using a Parallel Branching Program Machine. DSD (2010)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. IEICE Trans. Inf. Syst. (8) (2010)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
A virus scanning engine using a parallel finite-input memory machine and MPUs. FPL (2009)
Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura
Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. DSD (2009)
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL (2009)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
A Parallel Branching Program Machine for Emulation of Sequential Circuits. ARC (2009)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
The Parallel Sieve Method for a Virus Scanning Engine. DSD (2009)
Tsutomu Sasao, Munehiro Matsuura
An Implementation of an Address Generator Using Hash Memories. DSD (2007)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. ISMVL (2007)
Munehiro Matsuura, Tsutomu Sasao
BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions. J. Multiple Valued Log. Soft Comput. 13 (4-6) (2007)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
Design Methods of Radix Converters Using Arithmetic Decompositions. IEICE Trans. Inf. Syst. (6) (2007)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A CAM Emulator Using Look-Up Table Cascades. IPDPS (2007)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
On Designs of Radix Converters Using Arithmetic Decompositions. ISMVL (2006)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A fast logic simulator using a look up table cascade emulator. ASP-DAC (2006)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Design Algorithm for Sequential Circuits Using LUT Rings. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura
Average Path Length of Binary Decision Diagrams. IEEE Trans. Computers 54 (9) (2005)
Tsutomu Sasao, Munehiro Matsuura
BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. DAC (2005)
Tsutomu Sasao, Munehiro Matsuura
A method to decompose multiple-output logic functions. DAC (2004)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. ISMVL (2004)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
Evaluation of multiple-output logic functions using decision diagrams. ASP-DAC (2003)
Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
Comparison of Decision Diagrams for Multiple-Output Logic Functions. IWLS (2002)
Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi
Bi-Partition of Shared Binary Decision Diagrams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura
Representations of Logic Functions Using QRMDDs. ISMVL (2002)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
Realization of Multiple-Output Functions by Reconfigurable Cascades. ICCD (2001)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno
A hardware simulation engine based on decision diagrams (short paper). ASP-DAC (2000)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
Implementation of Multiple-Output Functions Using PQMDDs. ISMVL (2000)
Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno
Realization of Regular Ternary Logic Functions. ASP-DAC (1999)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
On properties of Kleene TDDs. ASP-DAC (1997)
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
On Decomposition of Kleene TDDs. Asian Test Symposium (1997)