IWLS

Keyphrases

Publications

2002

Tomas Bengtsson, Andrés Martinelli, Elena Dubrova
A Fast Heuristic Algorithm for Disjunctive. IWLS (2002)
Pawel Kerntopf
Nonlinear Sifting of Decision Diagrams. IWLS (2002)
Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli
Implicit Test of Regularity for Not Completely Specified Boolean Functions. IWLS (2002)
Jordi Cortadella
Bi-Decomposition and Tree-Height Reduction for Timing Optimization. IWLS (2002)
Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis
Comparing Transistor-Level Implementations of 4-Input Logic Functions. IWLS (2002)
Jorgiano Vidal, David Déharbe, Dominique Borrione
Improving Static Ordering of BDDs for Reachability Analysis. IWLS (2002)
Hua Tang, Alex Doboli
Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing. IWLS (2002)
Theodore W. Manikas, Gerald R. Kane
Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement. IWLS (2002)
DoRon B. Motter, Igor L. Markov
Overcoming Resolution-Based Lower Bounds for SAT Solvers. IWLS (2002)
Chang Woo Kang, Massoud Pedram
Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration. IWLS (2002)
Rajeev Murgai
Net Buffering in the Presence of Multiple Timing Views. IWLS (2002)
Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton
Low Power Optimization Techniques for BDD Mapped Finite State Machines. IWLS (2002)
Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain
Improving Sequential ATPG Using SAT Methods. IWLS (2002)
Amit Tandon, Federico Politi
Model Generation and Gate Level Abstraction of Complex CMOS Custom Design for Functional and DFT Validation. IWLS (2002)
Fan Mo, Robert K. Brayton
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. IWLS (2002)
Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS (2002)
Loïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan
A LUT based Approach for High Level Synthesis on FPGAs. IWLS (2002)
Anas Al-Rabadi
Symmetry as a Base for a New Decomposition of Boolean Logic. IWLS (2002)
Jaijeet S. Roychowdhury
Optical Systems 101 for EDA Practitioners. IWLS (2002)
Christoph Meinel, Christian Stangier
Modular Partitioning and Dynamic Conjunction Scheduling in Image Computation. IWLS (2002)
Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah
ZBDD-Based Backtrack Search SAT Solver. IWLS (2002)
Prabhakar Kudva, Andrew Sullivan, William E. Dougherty
Metrics for Structural Logic Synthesis. IWLS (2002)
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
High Throughput Asynchronous Domino Using Dual output Buffer. IWLS (2002)
Anas Al-Rabadi, Lee W. Casperson
Optical Realizations of Reversible Logic. IWLS (2002)
Afshin Abdollahi, Farzan Fallah
Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits. IWLS (2002)
Svetlana N. Yanushkevich, Vlad P. Shmerko, V. D. Malyugin, Piotr Dziurzanski
Linearity of World-Level Circuit Models: New Understanding. IWLS (2002)
Leyla Nazhandali, Karem A. Sakallah
Majority-Based Decomposition of Carry Logic in Binary Adders. IWLS (2002)
Christoph Meinel, Harald Sack, Volker Schillings
VisBDD - A Web-based Visualization Framework for OBDD Algorithms. IWLS (2002)
Geun Rae Cho, Tom Chen
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS (2002)
Nattawut Thepayasuwan, Alex Doboli
A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints. IWLS (2002)
Ankur Srivastava, Majid Sarrafzadeh
Predictability: Definition, Analysis and Optimization. IWLS (2002)
Jason Cong, Joey Y. Lin, Wangning Long
Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS (2002)
Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
Topologically Constrained Logic Synthesis. IWLS (2002)
Alan Mishchenko, Robert K. Brayton
A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS (2002)
Miodrag Vujkovic, Carl Sechen
Optimized Power-Delay Curve Generation for Standard Cell ICs. IWLS (2002)
Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala
On-line Error Detection in a Carry-free Adder. IWLS (2002)
Pawel Kerntopf
An Approach to Designing Complex Reversible Logic Gates. IWLS (2002)
Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
Reversible Logic Circuit Synthesis. IWLS (2002)
Federico Politi
Recognition of Transistor Level Complex Sequential and Dynamic Circuits using State Based BDD's. IWLS (2002)
Mohamed A. Elgamel, Magdy A. Bayoumi
On Low Power High Level Synthesis Using Genetic Algorithms. IWLS (2002)
Tiberiu Chelcea, Steven M. Nowick
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. IWLS (2002)
Silviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton
Synthesis of Morphable Multipliers. IWLS (2002)
Agnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev
Visualization of Coding Conflicts in Asynchronous Circuit Design. IWLS (2002)
Alexandre V. Bystrov, Alexandre Yakovlev
Synthesis of Asynchronous Circuits with Predictable Latency. IWLS (2002)
Farzan Fallah
Binary Time Frame Expansion. IWLS (2002)
Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera
Experimental Study on Cell-Base High-Performance Datapath Design. IWLS (2002)
Stephen A. Edwards
High-Level Synthesis from the Synchronous Language Esterel. IWLS (2002)
Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz
A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification. IWLS (2002)
Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
Reducing Multi-Valued Algebraic Operations to Binary. IWLS (2002)
Xinning Wang, Prashant Sawkar, Barbara A. Chappell
A Constructive Matching Algorithm for Library-Based Domino Technology Mapping. IWLS (2002)