Hiroki Nakahara

ORCID

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 67

Top Venues

ISMVL

IEICE Trans. Inf. Syst.

FPT

FPL

Publications

Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara
A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference. MCSoC (2023)
Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara
A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA. ARC (2023)
Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16 (1) (2023)
Kennichi Nakamura, Hiroki Nakahara
A Consideration on Ternary Adversarial Generative Networks. ISMVL (2023)
Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30 (2) (2022)
Wei Zhang, Ray Cheung, Yun Liang, Hiroki Nakahara
Message from the General Chair and Program Co-Chairs. FPT (2022)
Ryota Kayanoma, Hiroki Nakahara
Fast Interface with Ensemble Ternary Neural Network. ISMVL (2022)
Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara
Multilayer Perceptron Training Accelerator Using Systolic Array. IEICE Trans. Inf. Syst. (12) (2022)
Kennichi Nakamura, Hiroki Nakahara
Optimizations of Ternary Generative Adversarial Networks. ISMVL (2022)
Yun Liang, Hiroki Nakahara, Wei Zhang, Fubing Mao, Ray Cheung
Preface. FPT (2022)
Ryosuke Kuramochi, Hiroki Nakahara
A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA. IEICE Trans. Inf. Syst. (12) (2021)
Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara
A Multilayer Perceptron Training Accelerator using Systolic Array. APCCAS (2021)
Hiroki Nakahara, Takayuki Tanaka, Ichihiko Toyoda
A novel compact planar magic-T using CPS and microstrip-to-CPS transition. IEICE Electron. Express 18 (15) (2021)
Naoto Soga, Ryosuke Kuramochi, Hiroki Nakahara
+1-Valued Deep Neural Networks. ISMVL (2021)
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS (2021)
Naoto Soga, Shimpei Sato, Hiroki Nakahara
Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder. IEICE Trans. Inf. Syst. (8) (2021)
Masayuki Shimoda, Youki Sada, Hiroki Nakahara
FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. J. Signal Process. Syst. 93 (5) (2021)
Akira Jinguji, Shimpei Sato, Hiroki Nakahara
Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. IEICE Trans. Inf. Syst. (12) (2021)
Naoto Soga, Hiroki Nakahara
Design Method for an LUT Network-Based CNN with a Sparse Local Convolution. FPT (2020)
Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. (12) (2020)
Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara
Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops (2020)
Ryosuke Kuramochi, Hiroki Nakahara
An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks. FPL (2020)
Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT (2020)
Yuta Suzuki, Naoto Soga, Shimpei Sato, Hiroki Nakahara
A Table Look-Up Based Ternary Neural Network Processor. ISMVL (2020)
Hiroki Nakahara, Zhiqiang Que, Wayne Luk
High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. FCCM (2020)
Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk
R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. FPGA (2020)
Hiroki Nakahara
+1-valued SSS-Net: Uniform Shift, Channel Sparseness, and Channel Shuffle. ISMVL (2020)
Akira Jinguji, Shimpei Sato, Hiroki Nakahara
Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. FCCM (2020)
Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk
Optimizing Reconfigurable Recurrent Neural Networks. FCCM (2020)
Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara
An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. FPL (2019)
Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC (2019)
Akira Jinguji, Youki Sada, Hiroki Nakahara
Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA. FPL (2019)
Masayuki Shimoda, Youki Sada, Hiroki Nakahara
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. ARC (2019)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. (5) (2019)
Atsuki Munakata, Hiroki Nakahara, Shimpei Sato
Noise Convolutional Neural Networks and FPGA Implementation. ISMVL (2019)
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. (5) (2019)
Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato
An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA (2019)
Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL (2019)
Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig (2019)
Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara
A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. FPT (2019)
Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT (2018)
Hiroki Nakahara, Tsutomu Sasao
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. ISCAS (2018)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART (2018)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. ISMVL (2018)
Akira Jinguji, Shimpei Sato, Hiroki Nakahara
-Means Clustering Using a High-Level Synthesis Design. IEICE Trans. Inf. Syst. (2) (2018)
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53 (4) (2018)
Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. VLSI Circuits (2018)
Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara
A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). HEART (2018)
Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. FPT (2018)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL (2018)
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. FPGA (2018)
Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA. IEICE Trans. Inf. Syst. (2) (2018)
Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL (2018)
Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. ARC (2017)
Haruyoshi Yonekawa, Hiroki Nakahara
On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA. IPDPS Workshops (2017)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. FPT (2017)
Hiroki Nakahara, Tomoya Fujii, Shimpei Sato
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. FPL (2017)
Hiroki Nakahara, Akira Jinguji, Simpei Sato, Tsutomu Sasao
A Random Forest Using a Multi-valued Decision Diagram on an FPGA. ISMVL (2017)
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
All binarized convolutional neural network and its implementation on an FPGA. FPT (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
A memory-based realization of a binarized deep convolutional neural network. FPT (2016)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto
). J. Multiple Valued Log. Soft Comput. 26 (1-2) (2016)
Hiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato
An acceleration of a random forest classification using Altera SDK for OpenCL. FPT (2016)
Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya Ogawa
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope. ISMVL (2016)
Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (1) (2016)
Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. SIGARCH Comput. Archit. News 44 (4) (2016)
Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai
An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD. ISMVL (2015)
Hiroki Nakahara, Tsutomu Sasao
A deep convolutional neural network based on nested residue number system. FPL (2015)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. IEICE Trans. Inf. Syst. (2) (2015)
Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank. ARC (2015)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K). ISMVL (2014)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
) Machines. IEICE Trans. Inf. Syst. (9) (2014)
Kenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto
Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization. ISIC (2014)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs. J. Multiple Valued Log. Soft Comput. 23 (3-4) (2014)
Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai
An AWF digital spectrometer for a radio telescope. ReConFig (2014)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition. IEICE Trans. Inf. Syst. (8) (2013)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
An Architecture for IPv6 Lookup Using Parallel Index Generation Units. ARC (2013)
Hiroki Nakahara, Kazumasa Iwai, Hiroyuki Nakanishi
A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst. FPT (2013)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A packet classifier using LUT cascades based on EVMDDS (k). FPL (2013)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. ISMVL (2013)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. Microprocess. Microsystems 36 (8) (2012)
Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao
On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer. ICA3PP (1) (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. ARC (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. IEICE Trans. Inf. Syst. (2) (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. ISMVL (2012)
Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao
On a wideband fast fourier transform for a radio telescope. SIGARCH Comput. Archit. News 40 (5) (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. J. Multiple Valued Log. Soft Comput. 19 (1-3) (2012)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. ISMVL (2011)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Regular Expression Matching Circuit Based on a Decomposed Automaton. ARC (2011)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Comparison of Architectures for Various Decision Diagram Machines. ISMVL (2010)
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Trans. Inf. Syst. (8) (2010)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A Packet Classifier Using a Parallel Branching Program Machine. DSD (2010)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. IEICE Trans. Inf. Syst. (8) (2010)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
A virus scanning engine using a parallel finite-input memory machine and MPUs. FPL (2009)
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL (2009)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
A Parallel Branching Program Machine for Emulation of Sequential Circuits. ARC (2009)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
The Parallel Sieve Method for a Virus Scanning Engine. DSD (2009)
Tsutomu Sasao, Hiroki Nakahara
Implementations of Reconfigurable Logic Arrays on FPGAs. FPT (2007)
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
A CAM Emulator Using Look-Up Table Cascades. IPDPS (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

Hiroki Nakahara