Haruyoshi Yonekawa

Publication Activity (10 Years)

Years Active: 2016-2019
Publications (10 Years): 10

Top Topics

Fermentation Process

Top Venues

IEICE Trans. Inf. Syst.

Publications

Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. (5) (2019)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. ISMVL (2018)
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53 (4) (2018)
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. FPGA (2018)
Haruyoshi Yonekawa, Hiroki Nakahara
On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA. IPDPS Workshops (2017)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. FPT (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA (2017)
Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato
A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. FPL (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
A memory-based realization of a binarized deep convolutional neural network. FPT (2016)