Shinya Takamaeda-Yamazaki

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 50

Top Topics

Disparity Estimation

Fpga Implementation

Distributed Memory

Top Venues

IEICE Trans. Inf. Syst.

Publications

Tatsuya Kubo, Shinya Takamaeda-Yamazaki
Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems. IEEE Micro 44 (1) (2024)
Kotaro Shimamura, Shinya Takamaeda-Yamazaki
FS-Boost: Communication-Efficient Federated Subtree-Based Gradient Boosting Decision Trees. CCNC (2024)
Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. ASPDAC (2024)
Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. CoRR (2023)
Tatsuya Kubo, Shinya Takamaeda-Yamazaki
Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory. COOL CHIPS (2023)
Masayuki Usui, Shinya Takamaeda-Yamazaki
High-Level Synthesis of Memory Systems for Decoupled Data Orchestration. ARC (2023)
Sun Tanaka, Shinya Takamaeda-Yamazaki
MAO: Memory Architecture Obfuscation. MCSoC (2023)
Masayoshi Tsutsui, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki
Poison Egg: Scrambling Federated Learning with Delayed Backdoor Attack. UbiSec (2023)
Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka
HALO-CAT: A Hidden Network Processor with Activation-Localized CIM Architecture and Layer-Penetrative Tiling. CoRR (2023)
Yuki Hirayama, Kengo Suga, Shinya Takamaeda-Yamazaki
GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Network Accelerator with Gaussian Error Moment Propagation. MCSoC (2023)
Peiqi Zhang, Shinya Takamaeda-Yamazaki
MITA: Multi-Input Adaptive Activation Function for Accurate Binary Neural Network Hardware. IEICE Trans. Inf. Syst. 106 (12) (2023)
Masayoshi Tsutsui, Shinya Takamaeda-Yamazaki
SPinS-FL: Communication-Efficient Federated Subnetwork Learning. CCNC (2023)
Keisuke Kamahori, Shinya Takamaeda-Yamazaki
Accelerating Decision Tree Ensemble with Guided Branch Approximation. HEART (2022)
Peiqi Zhang, Shinya Takamaeda-Yamazaki
Multi-Input Adaptive Activation Function for Binary Neural Networks. CANDARW (2022)
Nobuho Hashimoto, Shinya Takamaeda-Yamazaki
FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. FPT (2022)
Nobuho Hashimoto, Shinya Takamaeda-Yamazaki
FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. CoRR (2022)
Yuki Hirayama, Shinya Takamaeda-Yamazaki
MP-GELU Bayesian Neural Networks: Moment Propagation by GELU Nonlinearity. CoRR (2022)
Sefutsu Ryu, Shinya Takamaeda-Yamazaki
Model-based Federated Reinforcement Distillation. GLOBECOM (2022)
Nobuho Hashimoto, Shinya Takamaeda-Yamazaki
An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. FPL (2021)
Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits 56 (1) (2021)
Yoshiki Fujiwara, Shinya Takamaeda-Yamazaki
ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design. ASAP (2021)
Nobuho Hashimoto, Shinya Takamaeda-Yamazaki
An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. CoRR (2021)
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. IEEE Access 9 (2021)
Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC (2020)
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS (2020)
Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. ARC (2020)
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. (12) (2019)
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits 54 (1) (2019)
Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR (2019)
Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
DeltaNet: Differential Binary Neural Network. ASAP (2019)
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. (12) (2019)
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT (2018)
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. IEICE Trans. Inf. Syst. (2) (2018)
Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC (2018)
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC (2018)
Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP (2018)
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53 (4) (2018)
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. 2018 (2018)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS (2017)
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR (2017)
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. FCCM (2017)
Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
Quantization Error-Based Regularization in Neural Networks. SGAI Conf. (2017)
Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Accelerating deep learning by binarized hardware. APSIPA (2017)
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL (2017)
Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
A Time-Division Multiplexing Ising Machine on FPGAs. HEART (2017)
Hoang Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing. CANDAR (2016)
Keisuke Fujimoto, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs. CANDAR (2016)
Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Thi Hong Tran, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. CANDAR (2016)
Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
Performance Optimization of Light-Field Applications on GPU. IEICE Trans. Inf. Syst. (12) (2016)
Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. IEICE Trans. Inf. Syst. (12) (2015)
Shohei Takeuchi, Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations. CANDAR (2015)
Shinya Takamaeda-Yamazaki
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. ARC (2015)
Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
A CGRA-Based Approach for Accelerating Convolutional Neural Networks. MCSoC (2015)
Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, Kenji Kise
Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs. IEICE Trans. Inf. Syst. (12) (2015)
Shinya Takamaeda-Yamazaki, Kenji Kise
flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. FPL (2014)
Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. CANDAR (2014)
Shinya Takamaeda-Yamazaki, Kenji Kise
A framework for efficient rapid prototyping by virtually enlarging FPGA resources. ReConFig (2014)
Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise
Ultrasmall: The smallest MIPS soft processor. FPL (2014)
Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise
Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations. ICNC (2012)
Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. ARC (2012)
Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, Kenji Kise
An FPGA-based scalable simulation accelerator for tile architectures. SIGARCH Comput. Archit. News 39 (4) (2011)