Junichiro Kadomoto

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 36

Top Topics

Collision Avoidance

Wireless Communication

Permalloy Films

Top Venues

Publications

Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System. CF (2024)
Masato Goto, Ibuki Sugiyama, Kenta Higuchi, Toshiki Goto, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication. CHI Extended Abstracts (2024)
Takashi Murayama, Shu Sugita, Hiroyuki Saegusa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs. UIST (Adjunct Volume) (2023)
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System. IEEE Des. Test 40 (6) (2023)
Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers. SPLASH Companion (2023)
Kenta Higuchi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces. SenSys (2023)
Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. MICRO (2023)
Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. ISCAS (2023)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus. SenSys (2023)
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Principal Factor of Performance in Decoupled Front-End. IEICE Trans. Inf. Syst. 106 (12) (2023)
Rin Oishi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
FPGA-based Garbling Accelerator with Parallel Pipeline Processing. IEICE Trans. Inf. Syst. 106 (12) (2023)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores. MCSoC (2022)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. ASP-DAC (2022)
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Compiling and Optimizing Real-world Programs for STRAIGHT ISA. ICCD (2021)
Junichiro Kadomoto, Takuya Sasatani, Koya Narumi, Naoto Usami, Hidetsugu Irie, Shuichi Sakai, Yoshihiro Kawahara
Toward Wirelessly Cooperated Shape-Changing Computing Particles. IEEE Pervasive Comput. 20 (3) (2021)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Multiport Register File Design for High-Performance Embedded Cores. MCSoC (2021)
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. ICCD (2021)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers. COOL CHIPS (2020)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces. AsianCHI@CHI (2020)
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
A High-Performance Out-of-Order Soft Processor Without Register Renaming. FPL (2020)
Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai
An Inductively Coupled Wireless Bus for Chiplet-Based Systems. ASP-DAC (2020)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. ICCD (2020)
Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. FPT (2019)
Ryosuke Takada, Junichiro Kadomoto, Buntarou Shizuki
A Sensing Technique for Data Glove Using Conductive Fiber. CHI Extended Abstracts (2019)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers. ICCD (2019)
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC (2018)
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. FPT (2018)
Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. 8 (1) (2018)
Akio Nomura, Junichiro Kadomoto, Tadahiro Kuroda, Hideharu Amano
A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface. CANDAR (2017)
Junichiro Kadomoto, Hideharu Amano, Tadahiro Kuroda
An inductive-coupling link for 3-D Network-on-Chips. ISOCC (2017)
Atsutake Kosuge, Junichiro Kadomoto, Tadahiro Kuroda
A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver. IEEE J. Solid State Circuits 51 (6) (2016)
Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda
An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. A-SSCC (2016)
So Hasegawa, Junichiro Kadomoto, Atsutake Kosuge, Tadahiro Kuroda
inductive-coupling side-by-side chip link. ESSCIRC (2016)
Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda
Analytical thruchip inductive coupling channel design optimization. ASP-DAC (2016)
Junichiro Kadomoto, So Hasegawa, Yusuke Kiuchi, Atsutake Kosuge, Tadahiro Kuroda
Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO. IEICE Trans. Electron. (6) (2016)
Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano
Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. CANDAR (2016)
Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda
A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Atsutake Kosuge, Shu Ishizuka, Junichiro Kadomoto, Tadahiro Kuroda
10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver. ISSCC (2015)