Ryota Shioya

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 39

Top Topics

Transactional Memory

Fine Granularity

Instruction Set

Top Venues

IEICE Trans. Inf. Syst.

Publications

Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
Branch Divergence-Aware Flexible Approximating Technique on GPUs. COOL CHIPS (2024)
Soramichi Akiyama, Ryota Shioya, Yuto Miyatake, Tongxin Yang
Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives. ISQED (2024)
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA. DATE (2023)
Tetsuro Yamazaki, Tomoki Nakamaru, Ryota Shioya, Tomoharu Ugawa, Shigeru Chiba
Collecting Cyclic Garbage across Foreign Function Interfaces: Who Takes the Last Piece of Cake? Proc. ACM Program. Lang. 7 (PLDI) (2023)
Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. MICRO (2023)
Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. ISCAS (2023)
Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima
Out-of-Step Pipeline for Gather/Scatter Instructions. DATE (2023)
Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. ASP-DAC (2023)
Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. CC (2023)
Yuichi Sugiyama, Reoma Matsuo, Ryota Shioya
SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs. ICCAD (2023)
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Principal Factor of Performance in Decoupled Front-End. IEICE Trans. Inf. Syst. 106 (12) (2023)
Naoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Ryota Shioya, Kei Ishii
PEZY-SC3: A MIMD Many-core Processor for Energy-efficient Computing. CoRR (2023)
Yasutaka Matsuda, Ryota Shioya, Hideki Ando
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison. IEICE Trans. Inf. Syst. (2) (2022)
Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
T-SKID: Predicting When to Prefetch Separately from Address Prediction. DATE (2022)
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Compiling and Optimizing Real-world Programs for STRAIGHT ISA. ICCD (2021)
Soramichi Akiyama, Ryota Shioya
The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout. ICPE (2021)
Soramichi Akiyama, Ryota Shioya
The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout. CoRR (2021)
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. ICCD (2021)
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
A High-Performance Out-of-Order Soft Processor Without Register Renaming. FPL (2020)
Susumu Mashimo, Ryota Shioya, Koji Inoue
Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core. HPC Asia (2020)
Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. FPT (2019)
Reoma Matsuo, Ryota Shioya, Hideki Ando
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. IEEE Comput. Archit. Lett. 18 (2) (2019)
Keita Doi, Ryota Shioya, Hideki Ando
Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications. J. Inf. Process. 26 (2018)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Bank-Aware Instruction Scheduler for a Multibanked Register File. J. Inf. Process. 26 (2018)
Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando
Rearranging Random Issue Queue with High IPC and Short Delay. ICCD (2018)
Susumu Mashimo, Ryota Shioya, Koji Inoue
VMOR: Microarchitectural Support for Operand Access in an Interpreter. IEEE Comput. Archit. Lett. 17 (2) (2018)
Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai
STRAIGHT: Hazardless Processor Architecture Without Register Renaming. MICRO (2018)
Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
An Analysis and a Solution of False Conflicts for Hardware Transactional Memory. ICECS (2018)
Ushio Jimbo, Ryota Shioya, Masahiro Goshima
Application of Timing Fault Detection to Rocket Core on FPGA. CANDAR Workshops (2018)
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. FPT (2018)
Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
Isolation-Safe Speculative Access Control for Hardware Transactional Memory. ICECS (2018)
Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. ARCS (2018)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. IEICE Trans. Inf. Syst. (4) (2017)
Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima
Applying Razor Flip-Flops to SRAM Read Circuits. IEICE Trans. Electron. (3) (2017)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. IEICE Trans. Electron. (3) (2017)
Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
Initial study of a phase-aware scheduling for hardware transactional memory. PACRIM (2017)
Ryota Shioya, Hideki Ando
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency. IEICE Trans. Inf. Syst. (3) (2016)
Hideki Ando, Ryota Shioya
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control. IEICE Trans. Inf. Syst. (2) (2016)
Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando
FXA: Executing Instructions in Front-End for Energy Efficiency. IEICE Trans. Inf. Syst. (4) (2016)
Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Address Order Violation Detection with Parallel Counting Bloom Filters. IEICE Trans. Electron. (7) (2015)
Ryota Shioya, Masahiro Goshima, Hideki Ando
A Front-End Execution Architecture for High Energy Efficiency. MICRO (2014)
Ryota Shioya, Hideki Ando
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. ICCD (2014)
Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai
Register Indirect Jump Target Forwarding. IEICE Trans. Inf. Syst. (2) (2013)
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Low-Overhead Architecture for Security Tag. IEICE Trans. Inf. Syst. (1) (2011)
Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Register Cache System Not for Latency Reduction Purpose. MICRO (2010)
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Low-Overhead Architecture for Security Tag. PRDC (2009)
Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
String-Wise Information Flow Tracking against Script Injection Attacks. PRDC (2009)
Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC (2006)