Hidetsugu Irie

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 37

Top Topics

Integrity Verification

Tightly Coupled

Wireless Communication

Dependency Graphs

Top Venues

IEICE Trans. Inf. Syst.

Publications

Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
Branch Divergence-Aware Flexible Approximating Technique on GPUs. COOL CHIPS (2024)
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System. CF (2024)
Masato Goto, Ibuki Sugiyama, Kenta Higuchi, Toshiki Goto, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication. CHI Extended Abstracts (2024)
Takashi Murayama, Shu Sugita, Hiroyuki Saegusa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs. UIST (Adjunct Volume) (2023)
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System. IEEE Des. Test 40 (6) (2023)
Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers. SPLASH Companion (2023)
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA. DATE (2023)
Kenta Higuchi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces. SenSys (2023)
Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. MICRO (2023)
Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. ISCAS (2023)
Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. CC (2023)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus. SenSys (2023)
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Principal Factor of Performance in Decoupled Front-End. IEICE Trans. Inf. Syst. 106 (12) (2023)
Rin Oishi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
FPGA-based Garbling Accelerator with Parallel Pipeline Processing. IEICE Trans. Inf. Syst. 106 (12) (2023)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores. MCSoC (2022)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. ASP-DAC (2022)
Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
T-SKID: Predicting When to Prefetch Separately from Address Prediction. DATE (2022)
Tomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai
Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation. ICCD (2021)
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Compiling and Optimizing Real-world Programs for STRAIGHT ISA. ICCD (2021)
Junichiro Kadomoto, Takuya Sasatani, Koya Narumi, Naoto Usami, Hidetsugu Irie, Shuichi Sakai, Yoshihiro Kawahara
Toward Wirelessly Cooperated Shape-Changing Computing Particles. IEEE Pervasive Comput. 20 (3) (2021)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Multiport Register File Design for High-Performance Embedded Cores. MCSoC (2021)
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. ICCD (2021)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers. COOL CHIPS (2020)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces. AsianCHI@CHI (2020)
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
A High-Performance Out-of-Order Soft Processor Without Register Renaming. FPL (2020)
Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai
An Inductively Coupled Wireless Bus for Chiplet-Based Systems. ASP-DAC (2020)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. ICCD (2020)
Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. FPT (2019)
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers. ICCD (2019)
Takahiro Yamada, Hidetsugu Irie, Masahiro Kunitake, Eiji Nagano, Shuichi Sakai
Estimating driver's readiness by understanding driving posture. ICCE (2018)
Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai
Reduction of Instruction Increase Overhead by STRAIGHT Compiler. CANDAR Workshops (2018)
Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai
STRAIGHT: Hazardless Processor Architecture Without Register Renaming. MICRO (2018)
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. FPT (2018)
Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai
Accelerating Integrity Verification on Secure Processors by Promissory Hash. PRDC (2017)
Takahiro Yamada, Hidetsugu Irie, Shuichi Sakai
High-Accuracy Joint Position Estimation and Posture Detection System for Driving. MobiQuitous (Adjunct Proceedings) (2016)
Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai
"Stubborn" strategy to mitigate remaining cache misses. ICCD (2016)
Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga
Design and Evaluation of a Configurable Query Processing Hardware for Data Streams. IEICE Trans. Inf. Syst. (12) (2015)
Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga
An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications. MCSoC (2014)
Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga
Accelerating OLAP Workload on Interconnected FPGAs with Flash Storage. CANDAR (2014)
Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga
An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA. CANDAR (2013)
Hirotaka Kashihara, Hiroki Shimizu, Hiroyoshi Houchi, Masato Yoshimi, Tsutomu Yoshinaga, Hidetsugu Irie
A real-time gait improvement tool using a smartphone. AH (2013)
Cisse Ahmadou Dit Adi, Michihiro Koibuchi, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga
A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation. IEICE Trans. Inf. Syst. (12) (2013)
Takuma Nakajima, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga
Sharing Computing Resources with Virtual Machines by Transparent Data Access. CANDAR (2013)
Takefumi Miyoshi, Hidetsugu Irie, Keigo Shima, Hiroki Honda, Masaaki Kondo, Tsutomu Yoshinaga
FLAT: a GPU programming framework to provide embedded MPI. GPGPU@ASPLOS (2012)
Hidetsugu Irie, Daisuke Fujiwara, Kazuki Majima, Tsutomu Yoshinaga
STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers. ICNC (2012)
Akira Egashira, Shunji Satoh, Hidetsugu Irie, Tsutomu Yoshinaga
Parallel Numerical Simulation of Visual Neurons for Analysis of Optical Illusion. ICNC (2012)
Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga
Using Cacheline Reuse Characteristics for Prefetcher Throttling. IEICE Trans. Inf. Syst. (12) (2012)
Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga
Throttling Control for Bufferless Routing in On-chip Networks. MCSoC (2012)
Junichi Ohmura, Akira Egashira, Shunji Satoh, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation. ICNC (2011)
Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. Int. J. Netw. Comput. 1 (2) (2011)
Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga
CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection. ICNC (2011)
Junichi Ohmura, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster. IEICE Trans. Inf. Syst. (12) (2011)
Qin Wang, Junichi Ohmura, Axida Shan, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga
Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster. ICNC (2010)
Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga
CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. ICNC (2010)
Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
An Efficient Path Setup for a Photonic Network-on-Chip. ICNC (2010)
Cisse Ahmadou Dit Adi, Ping Qiu, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip. IWIA (2010)
Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita
Low-Complexity Bypass Network Using Small RAM. CDES (2008)
Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie
Ultra Dependable Processor. IEICE Trans. Electron. (9) (2008)
Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai
Preventing timing errors on register writes: mechanisms of detections and recoveries. SIGARCH Comput. Archit. News 35 (5) (2007)
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Utilization of SECDED for soft error and variation-induced defect tolerance in caches. DATE (2007)
Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC (2006)