Masahiro Goshima

Publication Activity (10 Years)

Years Active: 1993-2023
Publications (10 Years): 15

Top Topics

Speculative Execution

Energy Efficiency

Transactional Memory

Top Venues

IEICE Trans. Inf. Syst.

IEICE Trans. Electron.

Publications

Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima
Out-of-Step Pipeline for Gather/Scatter Instructions. DATE (2023)
Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. FPT (2019)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Bank-Aware Instruction Scheduler for a Multibanked Register File. J. Inf. Process. 26 (2018)
Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
An Analysis and a Solution of False Conflicts for Hardware Transactional Memory. ICECS (2018)
Ushio Jimbo, Ryota Shioya, Masahiro Goshima
Application of Timing Fault Detection to Rocket Core on FPGA. CANDAR Workshops (2018)
Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
Isolation-Safe Speculative Access Control for Hardware Transactional Memory. ICECS (2018)
Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. ARCS (2018)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. IEICE Trans. Inf. Syst. (4) (2017)
Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima
Applying Razor Flip-Flops to SRAM Read Circuits. IEICE Trans. Electron. (3) (2017)
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. IEICE Trans. Electron. (3) (2017)
Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
Initial study of a phase-aware scheduling for hardware transactional memory. PACRIM (2017)
Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando
FXA: Executing Instructions in Front-End for Energy Efficiency. IEICE Trans. Inf. Syst. (4) (2016)
Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai
An Inductive Method to Select Simulation Points. IEICE Trans. Inf. Syst. (12) (2016)
Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
Address Order Violation Detection with Parallel Counting Bloom Filters. IEICE Trans. Electron. (7) (2015)
Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai
An Inductive Method to Select Simulation Points. CANDAR (2015)
Ryota Shioya, Masahiro Goshima, Hideki Ando
A Front-End Execution Architecture for High Energy Efficiency. MICRO (2014)
Koki Murakami, Tsuyoshi Yamada, Rie Shigetomi Yamaguchi, Masahiro Goshima, Shuichi Sakai
A cloud architecture for protecting guest's information from malicious operators with memory management. CODASPY (2014)
Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai
Register Indirect Jump Target Forwarding. IEICE Trans. Inf. Syst. (2) (2013)
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Low-Overhead Architecture for Security Tag. IEICE Trans. Inf. Syst. (1) (2011)
Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Register Cache System Not for Latency Reduction Purpose. MICRO (2010)
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
Low-Overhead Architecture for Security Tag. PRDC (2009)
Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
String-Wise Information Flow Tracking against Script Injection Attacks. PRDC (2009)
Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita
Low-Complexity Bypass Network Using Small RAM. CDES (2008)
Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie
Ultra Dependable Processor. IEICE Trans. Electron. (9) (2008)
Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai
Preventing timing errors on register writes: mechanisms of detections and recoveries. SIGARCH Comput. Archit. News 35 (5) (2007)
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Utilization of SECDED for soft error and variation-induced defect tolerance in caches. DATE (2007)
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
SEVA: A Soft-Error- and Variation-Aware Cache Architecture. PRDC (2006)
Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC (2006)
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. ICCD (2005)
Motohiro Takayama, Yuki Shinomoto, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita
Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing. PDPTA (2004)
Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori
A high-speed dynamic instruction scheduling scheme for superscalar processors. MICRO (2001)
Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR. Int. J. Parallel Program. 27 (2) (1999)
Shin-ya Goto, Atsushi Kubota, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR. IEEE PACT (1998)
Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR. ISHPC (1997)
Kazuhiko Ohno, Masahiko Ikawa, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, Masahiro Goshima
Improvement of message communication in concurrent logic language. PASCO (1997)
Kazuhiko Ohno, Masahiko Ikawa, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis. ASIAN (1997)
Shin-ichiro Mori, Masahiro Goshima, Hiroshi Nakashima, Shinji Tomita
A proposal of self-cleanup cache. PACT (1995)
Shin-ichiro Mori, Hideki Saito, Masahiro Goshima, Mamoru Yanagihara, Takashi Tanaka, David Fraser, Kazuki Joe, Hiroyuki Nitta, Shinji Tomita
A distributed shared memory multiprocessor ASURA: memory and cache architecture. SC (1993)