Yasuhiko Nakashima

ORCID

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 103

Top Venues

CANDAR

IEICE Trans. Inf. Syst.

COOL CHIPS

IEEE Access

Publications

Takumi Kuwahara, Reon Oshio, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
Fusion synapse by memristor and capacitor for spiking neuromorphic systems. Neurocomputing 593 (2024)
Van Duy Tran, Tran Xuan Hieu Le, Thi Diem Tran, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Tinh Nguyen, Yasuhiko Nakashima
Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation. CoRR (2024)
Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
A Compressed Spiking Neural Network Onto a Memcapacitive In-Memory Computing Array. IEEE Micro 44 (1) (2024)
Vu Trung Duong Le, Hoai-Luan Pham, Thi Hong Tran, Yasuhiko Nakashima
Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (3) (2024)
Mingyang Li, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
A Fully-Parallel Reconfigurable Spiking Neural Network Accelerator with Structured Sparse Connections. ISCAS (2024)
Pham Hoai Luan, Hai Hau Nguyen, Vu Trung Duong Le, Thi Diem Tran, Tuan Hai Vu, Thi Hong Tran, Yasuhiko Nakashima
MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements. COOL CHIPS (2024)
Yan Chen, Renyuan Zhang, Yirong Kan, Sa Yang, Yasuhiko Nakashima
Bisection Neural Network Toward Reconfigurable Hardware Implementation. IEEE Trans. Neural Networks Learn. Syst. 35 (3) (2024)
Dohyun Kim, Koki Asahina, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
Power-Efficient Acceleration of GCNs on Coarse-Grained Linear Arrays. COOL CHIPS (2024)
Reon Oshio, Takumi Kuwahara, Mutsumi Kimura, Yasuhiko Nakashima
Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory Computing. SOCC (2023)
Mutsumi Kimura, Yuma Ishisaki, Yuta Miyabe, Homare Yoshida, Isato Ogawa, Tomoharu Yokoyama, Ken-Ichi Haga, Eisuke Tokumitsu, Yasuhiko Nakashima
Neuromorphic System Using Memcapacitors and Autonomous Local Learning. IEEE Trans. Neural Networks Learn. Syst. 34 (5) (2023)
Tomoya Akabe, Ryotaro Funai, Yasuhiko Nakashima
Sensitivity Analysis of Memory Bandwidth on Column-superposed Versatile Linear CGRA. NEWCAS (2023)
Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
An Ultra-Compact Calculation Unit with Temporal-Spatial Re-configurability. NEWCAS (2023)
Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima
Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing. SOCC (2023)
Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima
High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing. MCSoC (2023)
Pham Hoai Luan, Thi Sang Duong, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima
Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain. MWSCAS (2023)
Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Diem Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran, Yasuhiko Nakashima
Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission. MCSoC (2023)
Vu Trung Duong Le, Hoai Luan Pham, Thi Sang Duong, Thi Hong Tran, Quoc Duy Nam Nguyen, Yasuhiko Nakashima
RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms. KSE (2023)
Hoai Luan Pham, Thi Hong Tran, Le Vu Trung Duong, Yasuhiko Nakashima
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications. IEEE Des. Test 40 (5) (2023)
Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Ren Imamura, Thi Hong Tran, Yasuhiko Nakashima
Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing. RIVF (2023)
Van-Cam Nguyen, Yasuhiko Nakashima
Implementation of Fully-Pipelined CNN Inference Accelerator on FPGA and HBM2 Platform. IEICE Trans. Inf. Syst. 106 (6) (2023)
Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima
Efficient and High-Speed CGRA Accelerator for Cryptographic Applications. candar (2023)
Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Quoc Duy Nam Nguyen, Thi Sang Duong, Yasuhiko Nakashima
Versatile Resource-shared Cryptographic Accelerator for Multi-Domain Applications. ICICDT (2023)
Babak Golbabaei, Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
A Non-deterministic Training Approach for Memory-Efficient Stochastic Neural Networks. SOCC (2023)
Shihori Akane, Isao Horiuchi, Yasushi Hiroshima, Yasuhiko Nakashima, Mutsumi Kimura
Phase-Change Memory using Cu2GeTe3 and Multiple Writing Technique for Neuromorphic Systems. ICCE (2023)
Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training. COOL CHIPS (2022)
Mutsumi Kimura, Hiroki Yamanaka, Yasuhiko Nakashima
Application of Machine Learning to Environmental DNA Metabarcoding. IEEE Access 10 (2022)
Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Yasuhiko Nakashima
CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining. SBCCI (2022)
Hoai Luan Pham, Thi Hong Tran, Le Vu Trung Duong, Yasuhiko Nakashima
A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration. IPDPS Workshops (2022)
Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima
A High-Efficiency FPGA-based BLAKE-256 Accelerator for Securing Blockchain Networks. MWSCAS (2022)
Hiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima
GPGPU Implementation of Variational Bayesian Gaussian Mixture Models. IEICE Trans. Inf. Syst. (3) (2022)
Hoai Luan Pham, Thi Hong Tran, Le Vu Trung Duong, Yasuhiko Nakashima
Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator. IEEE Access 10 (2022)
Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima
MuGRA: A Scalable Multi-Grained Reconfigurable Accelerator Powered by Elastic Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Guangxian Zhu, Huijia Wang, Yirong Kan, Zheng Chen, Ming Huang, Md. Altaf-Ul-Amin, Naoaki Ono, Shigehiko Kanaya, Renyuan Zhang, Yasuhiko Nakashima
A Stochastic Coding Method of EEG Signals for Sleep Stage Classification. SOCC (2022)
Hiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima
Application and Evaluation of Quantization for Narrow Bit-width Resampling of Sequential Monte Carlo. SOCC (2022)
Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
A Hybrid Bayesian-Convolutional Neural Network for Adversarial Robustness. IEICE Trans. Inf. Syst. (7) (2022)
Man Wu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima
GAND-Nets: Training Deep Spiking Neural Networks with Ternary Weights. SOCC (2022)
Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications. SBCCI (2022)
Hoai Luan Pham, Thi Hong Tran, Le Vu Trung Duong, Yasuhiko Nakashima
A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator. IEEE Access 10 (2022)
Van-Tinh Nguyen, Quang-Kien Trinh, Renyuan Zhang, Yasuhiko Nakashima
STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM. IEEE Access 9 (2021)
Thi Hong Tran, Hoai Luan Pham, Yasuhiko Nakashima
A High-Performance Multimem SHA-256 Accelerator for Society 5.0. IEEE Access 9 (2021)
Reon Oshio, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
Preliminary Evaluation for Multi-domain Spike Coding on Memcapacitive Neuromorphic Circuit. CANDAR (Workshops) (2021)
Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima
A Feasibility Study of Multi-Domain Stochastic Computing Circuit. IEICE Trans. Electron. (5) (2021)
Man Wu, Yirong Kan, Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima
DiaNet: An elastic neural network for effectively re-configurable implementation. Neurocomputing 464 (2021)
Van-Cam Nguyen, Yasuhiko Nakashima
Analysis of Fully-Pipelined CNN Implementation on FPGA and HBM2. CANDAR (Workshops) (2021)
Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks. IEICE Trans. Inf. Syst. (11) (2021)
Sugahara Takuya, Renyuan Zhang, Yasuhiko Nakashima
Training Low-Latency Spiking Neural Network through Knowledge Distillation. COOL CHIPS (2021)
Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima
High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory. COOL CHIPS (2021)
Van-Tinh Nguyen, Tieu-Khanh Luong, Emanuel M. Popovici, Quang-Kien Trinh, Renyuan Zhang, Yasuhiko Nakashima
An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic. MWSCAS (2021)
Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing. Integr. 77 (2021)
Le Vu Trung Duong, Thi Hong Tran, Hoai Luan Pham, Duc Khai Lam, Yasuhiko Nakashima
MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security. IEEE Access 9 (2021)
Thi Hong Tran, Hoai Luan Pham, Tri Dung Phan, Yasuhiko Nakashima
BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (10) (2021)
Tomoya Akabe, Renyuan Zhang, Yasuhiko Nakashima
Speeding Up of CGRAs by Reshaping and Stochastic FMA. CANDAR (Workshops) (2021)
Taku Honda, Hiroki Nishimoto, Yasuhiko Nakashima
Speeding Up VBGMM By Using Logsumexp With the Approximate Exp-function. CANDAR (Workshops) (2020)
Man Wu, Yan Chen, Yirong Kan, Takeshi Nomura, Renyuan Zhang, Yasuhiko Nakashima
An Elastic Neural Network Toward Multi-Grained Re-configurable Accelerator. NEWCAS (2020)
Hoai Luan Pham, Thi Hong Tran, Tri Dung Phan, Le Vu Trung Duong, Duc Khai Lam, Yasuhiko Nakashima
Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining. IEEE Access 8 (2020)
Ryuta Shingai, Yuria Hiraga, Hisakazu Fukuoka, Takamasa Mitani, Takashi Nakada, Yasuhiko Nakashima
Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing. IEICE Trans. Inf. Syst. (10) (2020)
Renyuan Zhang, Tati Erlina, Tinh Van Nguyen, Yasuhiko Nakashima
Hybrid Stochastic Computing Circuits in Continuous Statistics Domain. SoCC (2020)
Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima
A Multi-grained Reconfigurable Accelerator for Approximate Computing. ISVLSI (2020)
Jun Iwamoto, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima
Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth. IEICE Trans. Inf. Syst. (3) (2020)
Van-Tinh Nguyen, Tieu-Khanh Luong, Renyuan Zhang, Yasuhiko Nakashima
A Compact and Accuracy-Reconfigurable Univariate RBF Kernel Based on Stochastic Logic. ISCAS (2020)
Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
Bayes without Bayesian Learning for Resisting Adversarial Attacks. CANDAR (2020)
Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2019)
Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Yasuhiko Nakashima
Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems. CoRR (2019)
Renyuan Zhang, Yan Chen, Takashi Nakada, Yasuhiko Nakashima
DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon. SoCC (2019)
Van Tinh Nguyen, Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima
A Programmable Approximate Calculation Unit Employing Time-Encoded Stochastic Computing Elements. CANDAR Workshops (2019)
Mutsumi Kimura, Kenta Umeda, Keisuke Ikushima, Toshimasa Hori, Ryo Tanaka, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
Neuro-inspired System with Crossbar Array of Amorphous Metal-Oxide-Semiconductor Thin-Film Devices as Self-plastic Synapse Units. ICONIP (2) (2019)
Yan Chen, Jing Zhang, Yuebing Xu, Yingjie Zhang, Renyuan Zhang, Yasuhiko Nakashima
A ReRAM-Based Row-Column-Oriented Memory Architecture for Convolutional Neural Networks. IEICE Trans. Electron. (7) (2019)
Van-Cam Nguyen, Hoai Luan Pham, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima
Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract. IEEE ICBC (2019)
Yan Chen, Jing Zhang, Yingjie Zhang, Renyuan Zhang, Mutsumi Kimura, Yasuhiko Nakashima
A Programmable Calculation Unit Employing Memcapacitor-based Neuromorphic Circuit. NEWCAS (2019)
Dai Long Hoang, Thi Hong Tran, Yasuhiko Nakashima
Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah. ICCBN (2019)
Yan Chen, Jing Zhang, Yuebing Xu, Yingjie Zhang, Renyuan Zhang, Yasuhiko Nakashima
An efficient ReRAM-based inference accelerator for convolutional neural networks via activation reuse. IEICE Electron. Express 16 (18) (2019)
Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima
GPGPU Implementation of Variational Bayesian Gaussian Mixture Models. CANDAR (2019)
Tati Erlina, Yan Chen, Renyuan Zhang, Yasuhiko Nakashima
An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOS. ACM Great Lakes Symposium on VLSI (2019)
Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima
Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach. APCC (2019)
Hiroya Ikeda, Hiroki Yamane, Mutsumi Kimura, Yuki Shibayama, Yasuhiko Nakashima
Evaluation of Neuromorphic Hardware using Cellular Neural Networks and Oxide Semiconductors. IPDPS Workshops (2019)
Jun Iwamoto, Renyuan Zhang, Yasuhiko Nakashima
Evaluation of a Chained Systolic Array with High-Speed Links. CANDAR Workshops (2019)
Hiroya Ikeda, Hiroki Yamane, Yuki Shibayama, Mutsumi Kimura, Yasuhiko Nakashima
Evaluation of Letter Reproduction System Using Cellular Neural Network and Oxide Semiconductor Synapses by Logic Simulation. CANDAR Workshops (2018)
Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima
Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. IEICE Trans. Inf. Syst. (2) (2018)
Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima
Efficient Multitasking on FPGA Using HDL-Based Checkpointing. ARC (2018)
Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima
Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver. CoRR (2018)
Renyuan Zhang, Noriyuki Uetake, Takashi Nakada, Yasuhiko Nakashima
Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing. IEEE Micro 38 (6) (2018)
Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima
A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract. GLOBECOM Workshops (2018)
Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
A programmable analog calculation unit for vector computations. COOL CHIPS (2018)
Takahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima
EMAXVR: A programmable accelerator employing near ALU utilization to DSA. COOL CHIPS (2018)
Mutsumi Kimura, Kenta Umeda, Keisuke Ikushima, Toshimasa Hori, Ryo Tanaka, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
Hopfield Neural Network with Double-Layer Amorphous Metal-Oxide Semiconductor Thin-Film Devices as Crosspoint-Type Synapse Elements and Working Confirmation of Letter Recognition. ICONIP (7) (2018)
Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima
Neuromorphic Hardware Using Simplified Elements and Thin-Film Semiconductor Devices as Synapse Elements - Simulation of Hopfield and Cellular Neural Network -. ICONIP (6) (2017)
Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing. CANDAR (2017)
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. FCCM (2017)
Mutsumi Kimura, Ryohei Morita, Sumio Sugisaki, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
Cellular neural network formed by simplified processing elements composed of thin-film transistors. Neurocomputing 248 (2017)
Takamasa Mitani, Hisakazu Fukuoka, Yuria Hiraga, Takashi Nakada, Yasuhiko Nakashima
Compression and Aggregation for Optimizing Information Transmission in Distributed CNN. CANDAR (2017)
Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima
A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes. J. Commun. 12 (2) (2017)
Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima
Letter Reproduction Simulator for Hardware Design of Cellular Neural Network Using Thin-Film Synapses - Crosspoint-Type Synapses and Simulation Algorithm. ICONIP (2) (2016)
Mutsumi Kimura, Nao Nakamura, Tomoharu Yokoyama, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
Simplification of Processing Elements in Cellular Neural Networks - Working Confirmation Using Circuit Simulation. ICONIP (2) (2016)
Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, Yasuhiko Nakashima
ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system. COOL Chips (2016)
Masayoshi Fujii, Yuuki Sato, Tomoaki Tsumura, Yasuhiko Nakashima
Exploiting Bloom Filters for Saving Power Consumption of Auto-Memoization Processor. CANDAR (2016)
Hoang Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing. CANDAR (2016)
Hiromasa Kato, Thi Hong Tran, Yasuhiko Nakashima
ASIC design of a low-complexity K-best Viterbi decoder for IoT applications. APCCAS (2016)
Keisuke Fujimoto, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs. CANDAR (2016)
Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Thi Hong Tran, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. CANDAR (2016)

Yasuhiko Nakashima.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Yasuhiko Nakashima