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Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining.
Hoai Luan Pham
Thi Hong Tran
Tri Dung Phan
Le Vu Trung Duong
Duc Khai Lam
Yasuhiko Nakashima
Published in:
IEEE Access (2020)
Keyphrases
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hardware architecture
hardware implementation
hardware architectures
data mining
email
knowledge discovery
processing elements
block matching motion estimation
pattern recognition
associative memory
field programmable gate array
machine learning
information systems
signal processing
frequent patterns