Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth.
Jun IwamotoYuma KikutaniRenyuan ZhangYasuhiko NakashimaPublished in: IEICE Trans. Inf. Syst. (2020)
Keyphrases
- memory space
- systolic array
- memory bandwidth
- reconfigurable architecture
- external memory
- memory access
- data flow
- level parallelism
- processing power
- floating point
- parallel architecture
- memory requirements
- processing units
- parallel programming
- high efficiency
- commodity hardware
- cache misses
- hardware and software
- image processing
- limited resources
- parallel processing
- high accuracy
- data structure
- parallel computing
- xml documents