Hironori Nakajo

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 19

Top Topics

Discrete Wavelet Transformation

Top Venues

J. Inf. Process.

J. Inf. Sci. Eng.

Publications

Masashi Takemoto, Yasutake Masuda, Jingyong Cai, Hironori Nakajo
Learning Algorithm for LesserDNN, a DNN with Quantized Weights. SoICT (2023)
Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo
Implementation of a RISC-V SMT Core in an AI processor. SoICT (2022)
Hironori Nakajo
Editor's Message to Special Issue of Embedded Systems Engineering. J. Inf. Process. 29 (2021)
Hironori Nakajo
Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. 28 (2020)
Daichi Teruya, Hironori Nakajo
A Ruby-Based Hardware/Software Co-Design Environment with Functional Reactive Programming: Mulvery. IEICE Trans. Inf. Syst. (9) (2020)
Hironori Nakajo
Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. 28 (2020)
Kesevan Veloo, Hayate Kojima, Shogo Takata, Masashi Nakamura, Hironori Nakajo
Interactive Cultivation System for the Future IoT-Based Agriculture. CANDAR Workshops (2019)
Hironori Nakajo
Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. 27 (2019)
Ryota Yamashita, Daichi Teruya, Hironori Nakajo
Parallelization of Recursive Function in Ruby-Based High-Level Synthesis. FPT (2019)
Tran Viet Toan, Rin Nishikawa, Le Tien Thanh, Masashi Takemoto, Tran Van Hoai, Huynh Thi Thanh Binh, Hironori Nakajo
Cow estrus detection with low-frequency accelerometer sensor by unsupervised learning. SoICT (2019)
Yusuke Katoh, Hironari Yoshiuchi, Yoshio Murata, Hironori Nakajo
Operation in Partitioned Circuits with Scalable Hardware Mechanism. JCSSE (2018)
Jingyong Cai, Masashi Takemoto, Hironori Nakajo
Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices. GCCE (2018)
Le Tien Thanh, Rin Nishikawa, Masashi Takemoto, Huynh Thi Thanh Binh, Hironori Nakajo
Cow estrus detection via Discrete Wavelet Transformation and Unsupervised Clustering. SoICT (2018)
Jingyong Cai, Masashi Takemoto, Hironori Nakajo
A Deep Look into Logarithmic Quantization of Model Parameters in Neural Networks. IAIT (2018)
Hironori Nakajo
Editor's Message to Special Issue on Embedded Systems Engineering. J. Inf. Process. 26 (2018)
Yo Nishiyama, Yuko Sasaki, Yuki Hirai, Hironori Nakajo, Keiichi Kaneko
Fault-tolerant Routing based on Routing Capabilities in a Hyper-Star Graph. J. Inf. Sci. Eng. 34 (6) (2018)
Yuto Ishikawa, Keitaro Yanai, Keisuke Koike, Takefumi Miyoshi, Hironori Nakajo
Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool. HEART (2017)
Masashi Takemoto, Ryota Suzuki, Katsuhiko Umeno, Masayuki Yashiro, Tetsuya Ryuchi, Kohta Ohshima, Naoya Kitagawa, Hironori Nakajo
Performance evaluation of an SoC for the real-time lens-free imager RALFIE. GCCE (2017)
Masashi Takemoto, Ryota Suzuki, Katsuhiko Umeno, Masayuki Yashiro, Tetsuya Ryuchi, Kohta Ohshima, Naoya Kitagawa, Hironori Nakajo
Design of real-time advanced lens free imager. SoICT (2016)
Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning
Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage. RTCSA (2) (2011)
Hironori Nakajo, Keisuke Koike, Atsushi Ohta, Kohta Ohshima, Kaori Fujinami
Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices. ICNC (2011)
Noboru Tanabe, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe
A memory accelerator with gather functions for bandwidth-bound irregular applications. IA3@SC (2011)
Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning
Detecting water waste activities for water-efficient living. UbiComp (2011)
Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo
Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis. IEICE Trans. Inf. Syst. (12) (2011)
Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo
Parallelizing Hilbert-Huang Transform on a GPU. ICNC (2010)
Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo
An Effective Replacement Policy Focusing on Lifetime of a Cache Line. CDES (2010)
Noboru Tanabe, Hironori Nakajo
Acceleration for MPI derived datatypes using an enhancer of memory and network. IPDPS Workshops (2010)
Noboru Tanabe, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo
An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing. J. Supercomput. 51 (3) (2010)
Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo
Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. CDES (2009)
Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe
The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. PDPTA (2009)
Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo
Network Interface Architecture for Scalable Message Queue Processing. ICPADS (2009)
Yoshiyasu Ogasawara, Hironori Nakajo
An Effective Replacement Strategy of Cache Memory for an SMT Processor. DSD (2009)
Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita
Low-Complexity Bypass Network Using Small RAM. CDES (2008)
Noboru Tanabe, Hironori Nakajo
Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. PVM/MPI (2008)
Noboru Tanabe, Hironori Nakajo
An Enhancer of Memory and Network for Cluster and its Applications. PDCAT (2008)
Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks (2007)
Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA (2007)
Kenji Kise, Toshinori Sato, Hironori Nakajo
Introduction. SIGARCH Comput. Archit. News 35 (5) (2007)
Satoshi Watanabe, Yoshiyasu Ogasawara, Ippei Tate, Hirofumi Yano, Hironori Nakajo
Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. PDPTA (2007)
Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo
Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA (2006)
Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo
A Model of Implementable SMT Processor on FPGA. PDPTA (2006)
Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki
Implementation of PC Cluster System with Memory Mapped File by Commodity OS. PDPTA (2006)
Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe
DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. FPL (2006)
Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki
Development of a Thread Scheduler for SMT Processor Architecture. PDPTA (2005)
Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA (2005)
Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. ISHPC (2005)
Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT (2005)
Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA (2005)
Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano
A New Memory Module for Memory Intensive Applications. PARELEC (2004)
Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA (2004)
Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA (2003)
Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA (2003)
Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki
Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA (2003)
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Clust. Comput. 5 (1) (2002)
Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC (2002)
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
MEMOnet : Network interface plugged into a memory slot. CLUSTER (2000)
Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN (2000)
Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda
A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links. Int. J. Parallel Program. 28 (2) (2000)
Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano
Coherence Protocol for Home Proxy Cache on RHiNET. PDPTA (2000)
Hironori Nakajo, Hidekazu Tanaka, Yoshinori Nakanishi, Masaki Kohata, Yukio Kaneda
Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface. HPCN Europe (1998)
Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda
An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links. ISHPC (1997)
Hironori Nakajo, Satoshi Ohtani, Takashi Matsumoto, Masadi Kohata, Kei Hiraki, Yukio Kaneda
An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. International Conference on Supercomputing (1997)
Hironori Nakajo, Satoshi Ohtani, Yukio Kaneda
A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1. ICDCS (1996)
Hironori Nakajo, Takashi Matsumoto, Masaki Kohata, Hideo Matsuda, Kei Hiraki, Yukio Kaneda
High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. Parallel and Distributed Computing and Systems (1995)
Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN (1994)