Norito Kato

Publication Activity (10 Years)

Years Active: 2003-2005
Publications (10 Years): 0

Publications

Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki
Development of a Thread Scheduler for SMT Processor Architecture. PDPTA (2005)
Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA (2005)
Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA (2004)
Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA (2003)
Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA (2003)
Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki
Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA (2003)