Yoshiyasu Ogasawara

Publication Activity (10 Years)

Years Active: 2005-2009
Publications (10 Years): 0

Publications

Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo
Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. CDES (2009)
Yoshiyasu Ogasawara, Hironori Nakajo
An Effective Replacement Strategy of Cache Memory for an SMT Processor. DSD (2009)
Yong Xu, Tatsuya Hiramatsu, Kateryna Tarasenko, Toyoaki Nishida, Yoshiyasu Ogasawara, Takashi Tajima, Makoto Hatakeyama, Masashi Okamoto, Yukiko I. Nakano
A two-layered approach to communicative artifacts. AI Soc. 22 (2) (2007)
Satoshi Watanabe, Yoshiyasu Ogasawara, Ippei Tate, Hirofumi Yano, Hironori Nakajo
Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. PDPTA (2007)
Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo
Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA (2006)
Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo
A Model of Implementable SMT Processor on FPGA. PDPTA (2006)
Toyoaki Nishida, Kazunori Terada, Takashi Tajima, Makoto Hatakeyama, Yoshiyasu Ogasawara, Yasuyuki Sumi, Yong Xu, Yasser F. O. Mohammad, Kateryna Tarasenko, Taku Ohya, Tatsuya Hiramatsu
Toward Robots as Embodied Knowledge Media. IEICE Trans. Inf. Syst. (6) (2006)
Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA (2005)
Yoshiyasu Ogasawara, Masashi Okamoto, Yukiko I. Nakano, Yong Xu, Toyoaki Nishida
How to Make Robot a Robust and Interactive Communicator. KES (3) (2005)