Shinobu Miwa

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 15

Top Topics

Energy Efficient

Significantly Reduced

Parallel Tree Search

Top Venues

IEICE Trans. Inf. Syst.

Publications

Kohei Yoshida, Shinobu Miwa, Hayato Yamaki, Hiroki Honda
Analyzing the impact of CUDA versions on GPU applications. Parallel Comput. 120 (2024)
Shinobu Miwa, Shin'ichiro Matsuo
Analyzing the Performance Impact of HPC Workloads with Gramine+SGX on 3rd Generation Xeon Scalable Processors. SC Workshops (2023)
Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. ASP-DAC (2023)
Kohei Yoshida, Rio Sageyama, Shinobu Miwa, Hayato Yamaki, Hiroki Honda
Analyzing Performance and Power-Efficiency Variations among NVIDIA GPUs. ICPP (2022)
Shinobu Miwa, Ignacio Laguna, Martin Schulz
PredCom: A Predictive Approach to Collecting Approximated Communication Traces. IEEE Trans. Parallel Distributed Syst. 32 (1) (2021)
Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda
Evaluating architecture-level optimization in packet processing caches. Comput. Networks 181 (2020)
Shinobu Miwa, Masaya Ishihara, Hayato Yamaki, Hiroki Honda, Martin Schulz
Footprint-Based DIMM Hotplug. IEEE Trans. Computers 69 (2) (2020)
Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda
RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache. IEICE Trans. Inf. Syst. (12) (2020)
Giorgis Georgakoudis, Nikhil Jain, Takatsugu Ono, Koji Inoue, Shinobu Miwa, Abhinav Bhatele
Evaluating the Impact of Energy Efficient Networks on HPC Workloads. HiPC (2019)
Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda
Multi-Level Packet Processing Caches. COOL CHIPS (2019)
Yuta Inouchi, Hayato Yamaki, Shinobu Miwa, Tomoaki Tsumura
Functionally-Predefined Kernel: a Way to Reduce CNN Computation. PACRIM (2019)
Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda
Data prediction for response flows in packet processing cache. DAC (2018)
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. (12) (2016)
Satoshi Shindo, Momoka Ohba, Tomoaki Tsumura, Shinobu Miwa
Evaluation of Task Mapping on Multicore Neural Network Accelerators. CANDAR (2016)
Momoka Ohba, Satoshi Shindo, Shinobu Miwa, Tomoaki Tsumura, Hayato Yamaki, Hiroki Honda
Initial Study of Reconfigurable Neural Network Accelerators. CANDAR (2016)
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD (2015)
Shinobu Miwa, Hiroshi Nakamura
Profile-based power shifting in interconnection networks with on/off links. SC (2015)
Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD (2015)
Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
Design Aid of Multi-core Embedded Systems with Energy Model. Inf. Media Technol. 9 (4) (2014)
Shinobu Miwa, Sho Aita, Hiroshi Nakamura
Performance estimation of high performance computing systems with Energy Efficient Ethernet technology. Comput. Sci. Res. Dev. 29 (3-4) (2014)
Shinobu Miwa, Takara Inoue, Hiroshi Nakamura
Area-Efficient Microarchitecture for Reinforcement of Turbo Mode. IEICE Trans. Inf. Syst. (5) (2014)
Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa
Normally-off computing project: Challenges and opportunities. ASP-DAC (2014)
Shinobu Miwa, Charles Lefurgy
Evaluation of Core Hopping on POWER7. SIGMETRICS Perform. Evaluation Rev. 42 (3) (2014)
Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
Data-aware power management for periodic real-time systems with non-volatile memory. NVMSA (2014)
Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura
Performance modeling for designing NoC-based multiprocessors. RSP (2013)
Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
Predict-More Router: A Low Latency NoC Router with More Route Predictions. IPDPS Workshops (2013)
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE (2013)
Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Naoya Maruyama
Integrating Multi-GPU Execution in an OpenACC Compiler. ICPP (2013)
Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
McRouter: Multicast within a router for high performance network-on-chips. PACT (2013)
Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping. ICCD (2013)
Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura
Communication Library to Overlap Computation and Communication for OpenCL Application. IPDPS Workshops (2012)
Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
A novel power-gating scheme utilizing data retentiveness on caches. ACM Great Lakes Symposium on VLSI (2012)
Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI (2012)
Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED (2012)
Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita
A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth. J. Comput. Sci. Technol. 26 (2) (2011)
Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo
Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis. IEICE Trans. Inf. Syst. (12) (2011)
Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo
Parallelizing Hilbert-Huang Transform on a GPU. ICNC (2010)
Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo
An Effective Replacement Policy Focusing on Lifetime of a Cache Line. CDES (2010)
Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo
Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. CDES (2009)
Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita
Low-Complexity Bypass Network Using Small RAM. CDES (2008)
Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita
A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases. IEICE Trans. Inf. Syst. (4) (2008)
Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita
Optimal pipeline depth with pipeline stage unification adoption. SIGARCH Comput. Archit. News 35 (5) (2007)