Hiroki Noguchi

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 6

Top Topics

Highly Reliable

Memory Hierarchy

Top Venues

Publications

Xiaoyu Sun, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang
Write Endurance and Integrated Margin-Expansion Schemes. ISSCC (2024)
Yasuo Hayashibara, Masato Kubotera, Hayato Kambe, Gaku Kuwano, Dan Sato, Hiroki Noguchi, Riku Yokoo, Satoshi Inoue, Yuta Mibuchi, Kiyoshi Irie
RoboCup2022 KidSize League Winner CIT Brains: Open Platform Hardware SUSTAINA-OP and Software. RoboCup (2022)
Hiroki Noguchi, Shunichi Hienuki, Masaaki Fuse
Network theory-based accident scenario analysis for hazardous material transport: A case study of liquefied petroleum gas transport in japan. Reliab. Eng. Syst. Saf. 203 (2020)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT (2017)
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC (2016)
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC (2015)
Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD (2015)
Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". ASP-DAC (2014)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC (2014)
Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. VLSIC (2014)
Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition. ASP-DAC (2013)
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE (2013)
Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto
VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition. IEICE Trans. Electron. (4) (2011)
Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shinpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi
Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network. ICCCN (2011)
Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. ISQED (2011)
Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition. CICC (2011)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Data-Intensive Sound Acquisition System with Large-scale Microphone Array. J. Inf. Process. 19 (2011)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. Inf. Media Technol. 6 (2) (2011)
Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Data-Intensive Sound Acquisition System with Large-scale Microphone Array. Inf. Media Technol. 6 (2) (2011)
Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto
A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. IEICE Trans. Electron. (4) (2011)
Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Intelligent ubiquitous sensor network for sound acquisition. ISCAS (2010)
Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. FPL (2010)
Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Live demonstration: Intelligent ubiquitous sensor network for sound acquisition. ISCAS (2010)
Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto
Parallel-processing VLSI architecture for mixed integer linear programming. ISCAS (2010)
Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 34.7-mW quad-core MIQP solver processor for robot control. CICC (2010)
Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi
An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. SiPS (2009)
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design (2009)
Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system. INTERSPEECH (2009)
Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED (2009)
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A Dependable SRAM with 7T/14T Memory Cells. IEICE Trans. Electron. (4) (2009)
Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system. FPT (2008)
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED (2008)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Trans. Electron. (4) (2008)
Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. Very Large Scale Integr. Syst. 16 (6) (2008)
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Variation in Future Processes. IEICE Trans. Electron. (10) (2007)
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Scheme and DVS Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI (2007)
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)